參數(shù)資料
型號(hào)： AD9925BBCZ
廠商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁(yè)數(shù)： 3/96頁(yè)
文件大?。?/td> 1447K
代理商： AD9925BBCZ
AD9925
SPECIFICATIONS
Table 1.
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGES
AVDD (AFE Analog Supply)
TCVDD (Timing Core Analog Supply)
RGVDD (RG Driver)
HVDD (H1 to H4 Drivers)
DRVDD (Data Output Drivers)
DVDD (Digital)
V-DRIVER SUPPLY VOLTAGES
VDVDD (V-Driver Input Logic Supply)
VH1, VH2 (V-Driver High Supply for 3-Level Outputs)
VM1, VM2 (V-Driver Mid Supply for 3-Level and 2-Level Outputs)
VL1, VL2 (V-Driver Low Supply for 3-Level and 2-Level Outputs)
POWER DISSIPATION—AFETG Section Only (see Figure 9 for Power Curves)
36 MHz, 3.0 V Supply, 100 pF Load on Each H1 to H4 Output, 20 pF RG Load
Standby 1 Mode
Standby 2 Mode
Standby 3 Mode
Power from HVDD Only
1
Power from RGVDD Only
Power from AVDD Only
Power from TCVDD Only
Power from DVDD Only
Power from DRVDD Only
POWER DISSIPATION—V-Driver Section Only (VDVDD, VH, VL)
Normal Operation (VH = 15.0 V, VL = 7.5 V)
2
Standby 1 Mode
2
Standby 2 Mode
2
Standby 3 Mode
2
MAXIMUM CLOCK RATE (CLI)
Rev. A | Page 3 of 96
Min
–25
–65
2.7
2.7
2.7
2.7
2.7
2.7
2.7
10.5
–1.0
–10.0
36
Typ
3.0
3.0
3.0
3.0
3.0
3.0
3.0
15.0
0.0
–7.5
370
10
10
1
130
10
105
42
57
26
60
70
70
110
Max
+85
+150
3.6
3.6
3.6
3.6
3.6
3.6
3.6
16.0
+3.0
–6.0
Unit
°C
°C
V
V
V
V
V
V
V
V
V
V
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
MHz
2
The power dissipated by the V-driver circuitry depends on the logic states of the inputs as well as actual CCD operation; default dc values are used for each measure-
ment, in each mode of operation. Load conditions are described in the
Vertical Driver Specifications
section.
1
The total power dissipated by the HVDD supply may be approximated using the equation
Total HVDD Power
= [
C
LOAD
×
HVDD
×
Pixel Frequency
] ×
HVDD.
Reducing the H-loading and/or using a lower HVDD supply will reduce the power dissipation. C
LOAD
is the total capacitance seen by all H-outputs.
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