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參數(shù)資料
| 型號： | AD9925BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數(shù)： | 46/96頁 |
| 文件大小： | 1447K |
| 代理商： | AD9925BBCZ |
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AD9925
ADC
Rev. A | Page 46 of 96
The AD992
mized fo
(D
uses a 2 V in
for
AD
O
The optical black clamp loop is
l chain and to track
CCD’s black l
ter
black le
reg
255
r
in
turned on once per horizontal lin
to suit a particu
clamp
black clam
reg
stil
rmance ADC architecture, opti-
low power. Diff
is typically better than 0.5 LSB. The ADC
. See Figure 10, Figu
nd noise performanc
y a
r high sp
inearity
NL) performan
put r
, and Figure 13
s for the
e plot
typical linearit
9925.
ptical Black Clamp
used to remove residual offsets
low frequency variations in the
the optical blac
e ADC output is com
elected by the user
ister. The value can be programmed be
LSB in 256 st
esulting error
educe noise, and the correction value is applied to the ADC
put through a DAC. Normally, the optical black clamp loop is
in the signa
evel
ixel in-
val on each lin
vel referen
d with a fixed
clamp level
n 0 LSB and
iltered to
signal is f
e, but this loop can be updated
lar application. If external digital
he postprocessin
e disabled using Bit
p is disabled, the cla
e programmable off
set a
more slowly
ing is used
ping m
ister. When th
l be used to pr
optical
the OPRMODE
evel register may
djustment.
B pulse should be placed durin
lack pixels. It is recommended that the CLPOB pulse duration
b
be at least 20 pixels wide. Shorter
o track low freque
will b
e the H
sec
e CCD’s optical
g th
pulse widths may be used, but
ncy variations in the black level
orizontal Clam
ping and Blank
the ability t
e reduced. Se
tion for timing examples.
ing
The AD9925
E register valu
own in Figu
ve the output latc
d immediately fr
NTROL Register
ansparent. The data outputs can also be disabled (three stated)
tr
by setting the AFE CONTROL Reg
ta is latched using the DOUT
wn in Figure 55
1 and Figure 22. It is
transparent, so that t
the ADC. Programm
to a 1 will set th
Bit D4
im-
possible to
ata outputs are
the AFE
put latches
e out
ister Bit D3 to a 1.
The switchin
analog
om
edg
SH
but ex
D
lo
SHDLOC = 0, then DOUT PHAS
location of 12 or
the da
reg
puts can couple noise back to the
ze any switchi
UT PHASE register
g location, or up to
ther settings can pr
ecessary. It is recommended that the
is n
signal path. T
mended that the
e as the SHP sam
P sampling locati
perimentation
OUT PHASE location not occur between the SHD sampling
cation and 12 edges after the SHD location. For example, if
ec-
t to the same
es after the
e good results,
oduc
E should be set to an edge
greater. If adjustable phase is not required for
ta outputs, the output latch
ister 0x03, Bit [4].
ansparent using
The data output coding is normally straight binary, but the
oding may be changed to gray coding by setting the AFE
c
CONTROL Register Bit D5 to a
1.
5 uses high perfo
eed and
ce
ange
erential nonl
re 12
. During
e, th
ce, s
k (shielded) p
pare
in the
twee
eps. The r
during t
ay b
e loo
ovid
g, the AD9925
D2 in
mp l
The CLPO
Digital Data Outputs
digital output da
e, as sho
re 2
hes
om
PHAS
ing is sh
lea
vali
CO
. Output data t
also
he d
ing
g of the data out
o minimi
DO
plin
on. O
ng noise, it is r
be se
12 edg
can be left tr
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