參數(shù)資料
型號(hào)： AD9925BBCZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁數(shù)： 31/96頁
文件大小： 1447K
代理商： AD9925BBCZ
AD9925
Sweep Mode Operation
The AD9925 contains an additional mode of vertical timing
operation called sweep mode. This mode is used to generate a
large number of repetitive pulses that span across multiple HD
lines. One example of where this mode is needed is at the start
of the CCD readout operation. At the end of the image exposure,
but before the image is transferred by the sensor gate pulses, the
vertical interline CCD registers should be free of all charge. This
can be accomplished by quickly shifting out any charge using a
long series of pulses from the XV outputs. Depending on the
vertical resolution of the CCD, up to two or three thousand clock
cycles will be needed to shift the charge out of each vertical CCD
line. This operation will span across multiple HD line lengths.
Normally, the AD9925 vertical timing must be contained within
one HD line length, but when sweep mode is enabled, the HD
boundaries will be ignored until the region is finished. To enable
sweep mode within any region, program
gister to high.
re
Rev. A | Page 31 of 96
operation. The
e vertical sequence registers using the VPATREP
grammed in th
registers. This produces a pulse train of the appropriate length.
Normally, the pulse train is truncated at the end of the HD line
length, but with sweep mode enabled for this region, the HD
boundaries are ignored. In Figure 40, the sweep region occupies
23 HD lines. After the sweep mode region is completed in the
next region, normal sequence operation will resume. When usi
sweep mode, be sure to set the region boundaries to the appro-
priate lines (using the sequence change positions) to pre
sw
ng
vent the
eep operation from overlapping the next vertical sequence.
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region
may be configured into a multiplier region. This mode uses the
vertical pattern registers in a slightly different manner. Multiplier
mode can be used to support unusual CCD timing requirements,
such as vertical pulses that are wider than a single HD line length.
The start polarity and toggle positions are still used in the same
manner as the standard VPAT group programming, but the
VPATLEN is used differently. Instead of using the pixel counter
(HD counter) to specify the toggle position locations (VTOG1,
2, 3) of the VPAT group, the VPATLEN is multiplied with the
VTOG position to allow very long pulses to be generated. To
calculate the exact toggle position, counted in pixels after the
start position, use the following equation:
the appropriate SWEEP
Figure 40 shows an example of the sweep mode
number of vertical pulses needed depends on the vertical reso-
lution of the CCD. The XV output signals are generated using
the vertical pattern registers (shown in Table 15). A single pulse
is created using the polarity and toggle position registers. The
number of repetitions is then programmed to match the num-
ber of vertical shifts required by the CCD. Repetitions are pro-
VPATLEN
VTOG
Position
Toggle
Mode
Multiplier
×
=
Because the
VTOG
register is multiplied by
VPATLEN
, the
resolution of the toggle position placement is reduced. If
VPATLEN
= 4, then the toggle position accuracy will be reduc
to a 4-pixel step size, instead of a single pixel step size. Table 1
summarizes how the VPAT group registers are used in multi-
plier mode operation. In multiplier mode, the VPATREPO and
VPATREPE registers should always be programmed to the sam
value as the highest toggle position.
ed
6
e
peration. The
first toggle position is two, and the second toggle position is nine.
In nonmultiplier mode, this would cause the vertical sequence
to toggle at pixel 2 and then pixel 9 within a single HD line
ever, now toggle positions are multiplied by the VTPLEN = 4, so
the first toggle occurs at pixel count = 8, and the second toggle
occurs at pixel count = 36. Sweep mode has also been enable
to allow the toggle positions to cross the HD line boundaries.
. How-
d
Table 16. Multiplier MODE Register Parameters
Register
Length
MULTI
1 b
XVPOL
1 b
XVTOG1
12 b
XVTOG2
12 b
XVTOG3
12 b
VPATLEN
10 b
VPATREP
12 b
Range
High/Low
High/Low
0 to 4095 Pixel Location
0 to 4095 Pixel Location
0 to 4095 Pixel Location
0 to 1023 Pixels
0 to 4095
Description
High Enables Multiplier Mode.
Starting Polarity of XV Signal in Each VPAT Group.
First Toggle Position for XV Signal in Each VPAT Group.
Second Toggle Position for XV Signal in Each VPAT Group.
Third Toggle Position for XV Signal in Each VPAT Group.
Used as Multiplier Factor for Toggle Position Counter.
VPATREPE/VPATREPO Should Be Set to the Same Value as TOG2 or TOG3.
The example shown in Figure 41 illustrates this o
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