參數(shù)資料
型號(hào)： AD9925BBCZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁數(shù)： 55/96頁
文件大?。?/td> 1447K
代理商： AD9925BBCZ
AD9925
STANDBY MODE OPERATION
The AD9925 contains three different standby modes to optimize
the overall power dissipation in a particular application. Bits [1:0]
of the OPRMODE register control the power-down state of the
device:
Rev. A | Page 55 of 96
OPRMODE[1:0] = 00 = Normal Operation (Full Power)
OPRMODE[1:0] = 01 = Standby 1 Mode
OPRMODE[1:0] = 10 = Standby 2 Mode
OPRMODE[1:0] = 11 = Standby 3 Mode (Lowest Overall Power)
Table 34 and Table 35 summarize the operation of each power-
down mode. Note that the OUT_CONTROL register takes
priority over the standby 1 and standby 2 modes in determining
the digital output states, but the standby 3 mode takes priority
over OUT_CONTROL. Standby 3 mode has the lowest power
consumption and even shuts down the crystal oscillator circuit
between CLI and CLO. Thus, if CLI and CLO are being used
with a crystal to generate the master clock, this circuit will be
powered down and there will be no clock signal. When return-
ing from standby 3 mode to normal operation, the timing core
must be reset at least 500 μs after the OPRMODE register is
written to. This will allow sufficient time for the crystal circuit
to settle.
The XV and shutter outputs can also be programmed to hold a
specific value during any of the standby modes, as detailed in
Table 35.
Table 34. Standby Mode Operation
I/O Block
AFE
Timing Core
CLO Oscillator
CLO
H1
H2
H3
H4
RG
VD
HD
DCLK
DOUT
Standby 3 (Default)
1, 2
Off
Off
Off
High
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Low
Low
Low
Low
OUT_CONT= LO
2
No Change
No Change
No Change
Running
Low
High
Low
High
Low
VDHDPOL Value
VDHDPOL Value
Low
Low
Standby 2
3, 4
Off
Off
On
Running
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
VDHDPOL Value
VDHDPOL Value
Low
Low
Standby 1
3
,
4
Off
Off
On
Running
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Undefined in Master Mode
Undefined in Master Mode
Running if DCLK MODE =1
Low
1
To exit standby 3 mode, first write a 00 to OPRMODE[1:0], then reset the timing core after ~500 μs to guarantee proper settling of the oscillator.
2
Standby 3 mode takes priority over OUT_CONTROL for determining the output polarities.
3
These polarities assume OUT_CONT = High., because OUT_CONTROL = Low takes priority over standby 1 and standby 2 modes.
4
Standby 1 and standby 2 modes will set H and RG drive strength to minimum value (4.3 mA).
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