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參數資料
| 型號： | AD9925BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數： | 63/96頁 |
| 文件大小： | 1447K |
| 代理商： | AD9925BBCZ |
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AD9925
Table 39. VD/HD Register Map
Address Data Bit Content
20
[0]
21
[0]
22
[11:0]
[17:12]
23
[11:0]
Rev. A | Page 63 of 96
Register Description
VD/HD Master or Slave Timing (0 = Slave Mode).
VD/HD Active Polarity. 0 = Low and 1 = High.
Rising Edge Location for HD.
r VD.
Rising Edge Location fo
SCP0. Used for All Fields.
Default Value
0
0
0
0
0
Register Name
MASTER
VDHDPOL
HDRISE
VDRISE
SCP0
Table 40. Timing Core Register Map
Address Data Bit Content
30
[0]
31
[0]
[6:1]
[12:7]
32
[0]
[6:1]
[12:7]
33
[0]
[6:1]
[12:7]
34
[0]
[1]
Default Value
0
1
0
20
1
0
20
1
0
20
0
0
Register Name
CLIDIVIDE
H1POL
H1POSLOC
H1NEGLOC
H3POL
H3POSLOC
H3NEGLOC
RGPOL
RGPOSLOC
RGNEGLOC
H1RETIME
H3RETIME
Register Description
Divide CLI Input Clock by 2. 1 = Divide by 2.
H1 Polarity. 0: Inversion, 1: No Inversion.
H1 Positive Edge Location.
H1 Negative Edge Location.
H3 Polarity. 0: Inversion, 1: No Inversion.
H3 Positive Edge Location.
H3 Negative Edge Location.
RG Polarity. 0: Inversion, 1: No Inversion.
RG Positive Edge Location.
RG Negative Edge Location.
Retime H1/H3 HBLK to Internal H1/H3 Clocks. Preferred setting is 1
for each bit, which adds one cycle of delay to the programmed HBLK
toggle positions.
Drive Strength Control for H1.
0: Off.
1: 4.3 mA.
2: 8.6 mA.
3: 12.9 mA.
4: 17.2 mA.
5: 21.5 mA.
6: 25.8 mA.
7: 30.1 mA.
Drive Strength Control for H2 (Same Values as H1DRV).
Drive Strength Control for H3 (Same Values as H1DRV).
Drive Strength Control for H4 (Same Values as H1DRV).
Drive Strength Control for RG (Same Values as H1DRV).
SHP Sampling Location.
SHD Sampling Location.
DOUT Phase Control.
0: DCLK Tracks DOUTPHASE.
1: DCLK Does Not Track DOUTPHASE, Remains Fixed with Regards to
CLI
Data Output Delay (t
OD
) with Respect to DCLK.
0: No Delay, 1: ~4 ns, 2: ~8 ns, and 3: ~12 ns.
Controls HBLK Width as a Fraction of H1 to H4 Frequency.
0: same, 1: 1/2, 2: 1/4, 3: 1/6, 4: 1/8, 5: 1/10, 6: 1/12, and 7: 1/14.
35
[2:0]
[5:3]
[8:6]
[11:9]
[14:12]
[5:0]
[11:6]
[5:0]
[6]
[8:7]
1
1
1
1
1
24
0
0
0
2
H1DRV
H2DRV
H3DRV
H4DRV
RGDRV
SHPLOC
SHDLOC
DOUTPHASE
DCLKMODE
DOUTDLY
36
37
38
[2:0]
0
HBLKWIDTH
Table 41. CLPOB Masking Register Map
Address Data Bit Content
40
[11:0]
[23:12]
41
[11:0]
[23:12]
42
[11:0]
43
[11:0]
[12]
Default Value
FFF
FFF
FFF
FFF
FFF
FFF
0
Register Name
CLPMASK0
CLPMASK1
CLPMASK2
CLPMASK3
CLPMASK4
CLPMASK5
CLPMASKTYPE
Register Description
CLPOB Line Masking Line No. 0, or Mask0 Range, Start Line
CLPOB Line Masking Line No. 1, or Mask0 Range, End Line
CLPOB Line Masking Line No. 2, or Mask1 Range, Start Line
CLPOB Line Masking Line No. 3, or Mask1 Range, End Line
CLPOB Line Masking Line No. 4, or Mask2 Range, Start Line
CLPOB Line Masking Line No. 5, or Mask2 Range, End Line
0: CLPOB Line Masking, 1: Enable CLPOB Range Masking
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