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| 型號： | AD9925BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數(shù)： | 61/96頁 |
| 文件大小： | 1447K |
| 代理商： | AD9925BBCZ |
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AD9925
Updating New Register Values
The AD99 5’s internal register are updated at d
depe
on t
nt ty
Rev. A | Page 61 of 96
2
iffe
nding
he particular reg
pes of register u
. Table 36 summ
tes:
pda
four differe
1.
SCK U
as soo
ters, sh
functi
bounda
select r
SCK u
ted
: Some of the registers in Bank 1
h data bit
gray in the B
o not requi
as power-up
Addr 0x7F i
.
pdated
d
) is written. T
egister list, a
ng with the n
eset functions. T
k 1 and Bank
n Ban
VD U
field r
edge. B
current field will not be corrupted, and the new register
values will be applied to the next field. Bank 1 register up-
dates may be further delayed past the
using the UPDATE registe (Addr 0x19). Th will delay
dates t
in th
ost of the r
s in Bank 2, ar
dating these val
ank 1,
dated at the nex
at the next VD
ues
VD falling edge by
e field. Note th
VD up
field registers are not affected by the UPDATE register.
o any HD line
2
3.
SG Line Updated
: A few of the registers in Bank 1 are up-
f the SG active line, at the HD falling
dated at the end o
edge. These registers control t
SUBCK output will not upda
been completed. These regist
Bank 1 register list.
he SUBCK signal, so that the
te until after the SG line has
ers are crosshatched in the
d Bank 3, all of the vertical
equence registers (Addr 0x00
ing Addr 0×7F) are updated at
ill be used. For example, in
cted Region 1 to use Vertical
outputs. This means that a write
done to the same register, the last one done before SCP1
will be the one that is updated. Likewise, register writes to
any Vertical Sequence 5 registers will be updated at SCP2,
o any Vertical Sequence 8 registers will
and register writes t
be updated at SCP3.
Tab
le 36. R
r Update Loca
Register Bank
Bank 1 Only
Bank 1, Bank
ns
Update Type
SCK Update
VD Update
Description
Register is immediately updated
Register is updated at the VD falli
by using the UP
UPDATE reg
ister.
Register is u
pdated at the
Register is u
pdated at th
rent times,
arizes the
pda
n as the 24t
aded in
ons that d
ry, such
egister (
ister
are update
hese regis-
re used for
ext VD
he bank
2) is also
(D23
ank 1 r
re gati
and r
pdated
: M
egister
y up
2.
egisters in B
e up
as well as the
t VD falling
edge, the
at the Bank
4.
SCP Updated
: In Bank 2 an
pattern group and vertical s
through Addr 0xCF, exclud
the next SCP, where they w
Figure 77, this field has sele
Sequence 3 for the vertical
to any of the Vertical Sequence 3 registers, or any of the ver-
tical pattern group registers that are referenced by Vertical
Sequence 3, will be updated at SCP1. If multiple writes are
egiste
tio
d
d
when the 24
th
data bit (D23) is clocked in.
ng edge. VD updated registers in Bank 1 may be delayed further
nk 1. Bank 2 updates will not be affected by th
Addr 0x19 in Ba
e
2
DATE register at
SG Line Up
SCP Update
Bank 1 Only
Bank 2, Bank
HD falli
e next SC
ine.
dated
d
ng edge at the end of the SG active l
P when the register will be u
sed.
3
VD
REGION 0
HD
SCP 1
REGION 1
SCP 2
N 3
SCP 3
REGION 2
REGIO
XSG
SGLINE
SCP 0
SERIAL
WRITE
SCK
UPDATED
SCP 0
VD
UPDAT
S
UPD
ED
SG
UPDATED
CP
ATED
XV1 TO XV6
USE VSEQ2
USE VSEQ3
USE VSEQ5
USE VSEQ8
0
Figure 77. R
tions (
egister Update Loca
See Table 40 for Definitions)
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