參數(shù)資料
型號(hào)： AD9925BBCZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁(yè)數(shù)： 7/96頁(yè)
文件大?。?/td> 1447K
代理商： AD9925BBCZ
AD9925
TIMING SPECIFICATIONS
C
L
= 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f
CLI
= 36 MHz, unless otherwise noted.
Table 5.
Parameter
MASTER CLOCK, CLI (Figure 17)
CLI Clock Period
CLI High/Low Pulse Width
Delay from CLI Rising Edge to Internal Pixel Position 0
AFE CLPOB PULSE WIDTH
1, 2
(Figure 23 and Figure 29)
AFE SAMPLE LOCATION
1
(Figure 20)
SHP Sample Edge to SHD Sample Edge
DATA OUTPUTS (Figure 21 and Figure 22)
Output Delay from DCLK Rising Edge, Default Value
1
Inhibited Area for DOUTPHASE Edge Location
1
Pipeline Delay from SHP/SHD Sampling to DOUT
SERIAL INTERFACE (Figure 74 and Figure 75)
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
Rev. A | Page 7 of 96
Symbol
t
CONV
t
CLIDLY
t
S1
t
OD
t
DOUTINH
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
DV
Min
27.8
11.2
2
12.5
SHDLOC
11
36
10
10
10
10
10
Typ
13.9
6
20
13.9
8
Max
16.6
SHDLOC + 11
Unit
ns
ns
ns
Pixels
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns
1
Parameter is register-programmable.
2
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
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