參數(shù)資料
型號(hào)： AD9925BBCZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁(yè)數(shù)： 32/96頁(yè)
文件大小： 1447K
代理商： AD9925BBCZ
AD9925
Rev. A | Page 32 of 96
VD
XV1 TO XV8
HD
REGION 1: SWEEP REGION
LINE 0
LINE 1
REGION 0
REGION 2
LINE 24
LINE 25
LINE 2
SCP 1
SCP 2
0
Figure 40. Example of Sweep Region for High Speed Vertical Shift
XV1 TO XV8
VPATLEN
MULTIPLIER MODE VERTICAL PATTERN GROUP PROPER
1. START POLARITY (ABOVE: STARTPOL =
2. FIRST, SECOND, AND THIRD TOGGLE PO
3. LENGTH OF VPAT COUNTER (ABOVE: VPATLEN = 4); THI
4. TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VT
HD
TIES:
0).
SITIONS (ABOVE: VTOG1 = 2
S IS THE MIN
OG × VPAT
AY ALSO C
, VTOG2 = 9).
IMUM RESOLUTION FOR TOGGLE POSITION CHANGES.
LEN).
ROSS THE HD BOUNDRIES, AS SHOWN ABOVE.
5. IF SWEEP REGION IS ENABLED, THE VERTICAL PULSES M
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
NUPIXEL
1
2
3
4
START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE VERTICAL SEQUENCE REGISTERS
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 1
3
5
4
1
2
7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
5
2
4
0
for Wide Vertical Pulse Timing
iplier Region
Figure 41. Example of Mult
Vertical Sensor Gate (Shift Gate) Patterns
an interline CCD, the sensor gates (SG) are used to transfer
In
the pixel charges from the light-sensitive image area into the
light-shielded ve
l registers. From he light-shielded vertical
registers, the image
vertical transfe
es in conjunction with the high
zontal clocks.
rtica
t
is then clocked out line-by-line, using the
r puls
spe
ns the
SG o
he
o XSG6. E
iste
the o
can be assigned to one of four programmed patterns by using
the SGPATSEL registers. Each pattern is generated in a similar
manner as the vertical pattern groups, with a programmable
start polarity (SGPOL), first toggle position (SGTOG1), and
second toggle position (SGTOG2). The active line where the SG
pulses occur is programmable using the SGLINE1 and
SGLINE2 registers. Additionally, any of the XSG1 to XSG6
outputs may be individually disabled by using the SGMASK
register. The individual masking allows all of the SG patterns to
ppr
fields can be separately enabled. For maximum flexibility, the
M
ble f
. Se
Sequ
n f
ing Vertical
ences sectio
or more deta
fo
nt
lete
ils.
in-
he
-
rides the SG masking in the field registers (Bank 2). The
SGMASK_OVR register allows sensor gate masking to be
changed without modifying the field register values. Setting the
SGMASKOVR_EN bit high enables the SGMASK override
function. The SGMASK_OVR register is SCK updated, so the
new SG masking values will update immediately.
ed hori-
Table 17 con
AD9925 has six
tai
summary of t
utputs, XSG1 t
SG pattern reg
ach of
rs. The
utputs
be preprogram ed, and the a
opriate pulses
r the differe
SGPATSEL, SG ASK, and SG INE registers are separately
programma
or each field
e the Comp
Field: Comb
Additionally, t
re is a register n Bank 1 (Add 0x55) that over
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