參數(shù)資料
型號: AD9925BBCZ
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝: 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁數(shù): 30/96頁
文件大小: 1447K
代理商: AD9925BBCZ
AD9925
Generating Line Alternat
HBLK
During low resolution readout, some CCDs require a different
number of vertical clocks on alternate lines. The AD9925 can
support this by using the VPATREPO and VPATREPE registers
This allows a different number of VPAT repetitions to be pro-
grammed on odd and even lines. Note that only the number of
repeats can be different in odd and even lines, but the VPAT
group remains the same.
Rev. A | Page 30 of 96
ion for Vertical Sequence and
.
nation used together. It is also possible to use
the VPAT and HBLK alternation separately.
attern Group during VSG Active Line
Second Vertical P
Most CCDs require additional vertical timing during the senso
gate (SG) line. The AD9925 supports the option to output a
second vertical pattern group for XV1 to XV8 during the line
when the sensor gates XSG1 to XSG6 are active. Figure 39 shows
a typical SG line that includes two separate sets of vertical pattern
group for XV1 to XV6. The vertical pattern group at the start of
the SG line is selected in the same manner as the other regions,
using the appropriate VSEQSEL register. The second vertical
pattern group, unique to the SG line, is selected using the
VPATSECOND register, located with the field registers. The
start position of the second VPAT group uses the VPATLEN
register from the selected VPAT registers. Because the VPATLE
register is used as the start position and not as the VPAT lengt
it is not possible to program multiple repet
r
N
h,
itions for the second
VPAT group.
Additionally, the HBLK signal can also be alternated for odd
and even lines. When the HBLKALT register is set high, the
HBLK TOG1 and HBLK TOG2 positions will be used on odd
lines, and the HBLK TOG3 to HBLK TOG6 positions will be
used on even lines. This allows the HBLK interval to be adjusted
on odd and even lines if needed.
Figure 38 shows an example of a VPAT repetition alternation
and a HBLK alter
XV1
XV2
VPATREPO = 2
XV6
HD
VPATREPE = 5
NOTES
1. THE NUMBER OF REPEATS FOR THE VERTICAL PATTERN GROUP MAY B
2. THE HBLK TOGGLE POSITIONS MAY BE ALTERNATED BETWEEN ODD AN
GENERATE DIFFERENT HBLK PATTERNS FOR ODD/EVEN LINES.
VPATREPO = 2
E ALTERN
D EVEN LI
ATED ON ODD AND EVEN LINES.
NES, IN ORDER TO
HBLK
TOG1
TOG2
TOG3
TOG4
TOG1
TOG2
0
Figure 38. Odd/Even Line Alteration of VPAT Repetitions and HBLK Toggle Positions
XV1
XV2
XV6
HD
XSG
SECOND VPAT GROUP
OR SECOND VPAT GROUP
GISTER
START POSITION F
USES VPATLEN RE
0
Figure 39. Example of Second VPAT Group during Sensor Gate Line
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