參數(shù)資料
型號(hào)： AD9925BBCZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁數(shù)： 14/96頁
文件大?。?/td> 1447K
代理商： AD9925BBCZ
AD9925
SYSTEM OVERVIEW
Figure 14 shows the typical system block diagram for the
AD9925 used in master mode. The CCD output is processed
the AD9925’s AFE circuitr
black level clamp, and ADC. The digitized pixel informa
sent to the digital image processor chip, which performs the
postprocessing and compression. To operate the CCD, all CCD
timing parameters are programmed into the AD9925 from the
system microprocessor through the 3-wire serial interface.
From the system master clock, CLI, provided by the image
processor or external crystal, the AD9925 generates the CCD’s
horizontal and vertical clocks and internal AFE clocks. E
synchronization is provided by a SYNC pulse from the micro
Rev. A | Page 14 of 96
by
y, which consists of a CDS, VGA,
tion is
xternal
-
processor, which will reset internal counters and resync the VD
and HD outputs. The AD9925 also contains an optional reset
pin, RSTB, which may be used to perform an asynchronous
hardware reset function.
CCDIN
MSHUT
STROBE
H1 TO H4, RG
V1A, V2, V3A, V3B, V4, V5A,
V5B, V6, V7, V8, SUBCK, VSUB
CCD
AD9925
AFETG
+
V-DRIVER
DIGITAL
IMAGE
PROCESSING
ASIC
DOUT
DCLK
HD, VD
CLI
SERIAL
INTERFACE
SYNC
RSTB
0
μ
P
Figure 14. Typical System Block Diagram, Master Mode
AD9925, allowing these clocks t
CCD. An H-d
voltage V-driver is also included for the vertical clocks, allowing
irect connection to the CCD. The SUBCK and VSUB signals
ay require external transistors, depending on the CCD used.
m
directly connected to the
d. A high
The AD9925 also includes programmable MSHUT and
STROBE outputs, which may be used to trigger mechanical
shutter and strobe (flash) circuitry.
Figure 15 and Figure 16 show the maximum horizontal and
vertical counter dimensions for the AD9925. All internal hori-
zontal and vertical clocking is controlled by these counters to
specify line and pixel locations. Maximum HD length is 8192
pixels per line, and maximum VD length is 4096 lines per field.
Alternatively, the AD9925 may be operated in slave mode, in
which the VD and HD are provided externally from the image
processor. In this mode, all AD9925 timing will be synchro-
nized with VD and HD.
The H-drivers for H1 to H4 and RG are included in the
o be
rive voltage of up to 3.3 V is supporte
d
13-BIT HORIZONTAL = 8192 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
MAXIMUM
COUNTER
DIMENSIONS
0
Figure 15. Vertical and Horizontal Counters
VD
HD
MAX VD LENGTH IS 4096 LINES
CLI
MAX HD LENGTH IS 8192 PIXELS
0
Figure 16. Maximum VD/HD Dimensions
相關(guān)PDF資料
PDF描述
AD9927 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator
AD9927BBCZ 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator
AD9927BBCZRL 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator
AD9929BBCZ CCD Signal Processor with Precision Timing Generator
AD9929 CCD Signal Processor with Precision Timing Generator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9925BBCZRL 制造商:Analog Devices 功能描述:IC 12-BIT SIGNAL PROCESSOR
AD9925KBCZ 制造商:Analog Devices 功能描述:12 BIT, 36 MSPS CCD SIGNAL PROCESSOR W/VERTICAL DRIVER - Bulk
AD9926BBCZ 制造商:Analog Devices 功能描述:
AD9926BBCZRL 制造商:Analog Devices 功能描述:
AD9927 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator
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