參數(shù)資料
型號(hào)： AD9925BBCZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁(yè)數(shù)： 76/96頁(yè)
文件大?。?/td> 1447K
代理商： AD9925BBCZ
AD9925
Table 58. Vertical Sequence 0 (VSEQ0) Register Map
Address Data Bit Content Default Value
80
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[12]
[23:12]
81
[11:0]
[23:12]
Rev. A | Page 76 of 96
e
n
Register Nam
HBLKMASK_0
CLPOBPOL_0
PBLKPOL_0
VPATSEL_0
VMASK_
Register Descriptio
Masking Polarity during HBLK. H1 [0], H3 [1
CLPOB Start Polarity
PBLK Start Polarity
Selected Vertical Pattern Group for Vertical Sequence 0
Enable Masking of Vertical Outputs (Specified by FREEZE/RESUM
Registers
Enable HBLK Alternation
13
th
Bit for HD Length Counter Allows HD Length up to 8191 Pixel
Unused
Number of Selected Vertical Pattern Group Repetitions for Odd Lines.
Number of Selected Vertical Pattern Group Repetitions for Even
Lines.
Start Position in the Line for the Selected Vertical Pattern
HD Line Length (Number of Pixels) for Vertical
PBLK Toggle Position 1 for Vertical Sequence 0
PBLK Toggle Position 2 for Vertical Sequence 0
HBLK Toggle Position 1 for Vertical Sequence
HBLK Toggle Position 2 for Vertical Sequence 0
HBLK Toggle Position 3 for Vertical Sequence
HBLK Toggle Position 4 for Vertical Sequence 0
HBLK Toggle Position 5 for Vertical Sequence 0
HBLK Toggle Position 6 for Vertical Sequence 0.
CLPOB Toggle Position 1 for Vertical Sequence 0
X
X
X
X
X
X
X
HBLKALT_
HDLEN13_0
UNUSED
VPATREPO_0
VPATREPE_
0
0
].
.
.
.
E
).
.
s.
.
X
X
0
82
RT_0
Group.
Sequence 0.
.
.
0.
.
0.
.
.
.
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
X
X
X
X
X
X
X
X
X
X
X
VPATSTA
HDLEN_0
PBLKTOG1_0
PBLKTOG2_0
HBLKTOG1_0
HBLKTOG2_0
HBLKTOG3_0
HBLKTOG4_0
HBLKTOG5_0
HBLKTOG6_0
CLPOBTOG1_0
83
84
85
86
87
[23:12]
X
CLPOBTOG2_0
CLPOB Toggle Position 2 for Vertical Sequence 0.
Table 59. Vertical Sequence 1
ress
Add
Data B
88
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[12]
[23:12]
89
[11:0]
[23:12]
8A
[11:0]
[23:12]
8B
[11:0]|
[23:12]
8C
[11:0]
[23:12]
8D
[11:0]
[23:12]
8E
[11:0]
[23:12]
8F
[11:0]
[23:12]
it Content
fault Value
De
X
X
X
X
X
(VSEQ1) Regist r Map
Register Nam
HBLKMASK_
CLPOBPOL
PBLKPOL_1
VPATSEL_1
VMASK_1
HBLKAL
HDLEN13_1
UNUSED
VPATREPO_1
VPATREPE_1
VPATSTART_
HDLEN_1
PBLKTOG1_1
PBLKTOG2_1
HBLKTOG1_1
HBLKTOG2_1
HBLKTOG3_1
HBLKTOG4_1
HBLKTOG5_1
HBLKTOG6_1
CLPOBTOG1_1
CLPOBTOG2_1
Register Description
Masking Polarity du
CLPOB Start Polar
PBLK Start Polarity.
Selected Vertical Pattern Group for Vertical Sequence 1.
Enable Masking of Verti
Registers).
Enable
13
th
Bit for HD Length Counter Allows HD Length up to 8191 Pixels.
Unused.
Number of Selected Vertical Pattern Group Repetitions for Odd
Number of Selected Vertical Pattern Group Repetitions for Eve
Start Position in the Line for the Selected Verti
HD Line Length (Number of Pixels) for Vertical
PBLK Toggle Position 1 for Vertical Sequence 1
PBLK Toggle Position 2 for Vertical Sequence 1
HBLK Toggle Position 1 for Vertical Sequence 1
HBLK Toggle Position 2 for Vertical Sequence 1
HBLK Toggle Position 3 for Vertical Sequence 1
HBLK Toggle Position 4 for Vertical Sequence 1.
HBLK Toggle Position 5 for Vertical Sequence 1.
HBLK Toggle Position 6 for Vertical Sequence 1.
CLPOB Toggle Position 1 for Vertical Sequence 1.
CLPOB Toggle Position 2 for Vertical Sequence 1.
X
X
1
_1
T_1
ring HBLK. H1 [0], H3 [1].
ity.
cal Outputs (Specified by FREEZE/RESUME
HBLK Alternation.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Lines.
n Lines.
1
cal Pattern Group.
Sequence 1.
.
.
.
.
.
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