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型號(hào)：	UPD780076
廠商：	NEC Corp.
元件分類：	8位微控制器
英文描述：	8-Bit Single-Chip Microcontrollers
中文描述：	8位單芯片微控制器
文件頁(yè)數(shù)：	73/592頁(yè)
文件大小：	3307K
代理商：	UPD780076

CHAPTER 5 CPU ARCHITECTURE

s Manual U14260EJ3V1UD

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledgment operations of the CPU.

When IE is 0 the interrupt disabled (DI) state is set, and only non-maskable interrupt requests become

acknowledgeable. Other interrupt requests are all disabled.

When IE is 1 the interrupt enabled (EI) state is set and interrupt request acknowledgment enable is controlled

by the in-service priority flag (ISP), the interrupt mask flag corresponding to each interrupt source and the

priority specification flag.

IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction

(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

These are 2-bit flags used to select one of the four register banks.

The 2-bit information which indicates the register bank selected by SEL RBn instruction execution is stored

in these flags.

(d) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other

(e) In-service priority flag (ISP)

This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-

level vectored interrupt requests specified by the priority specification flag register (PR0L, PR0H, PR1L)

19.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L)

) are disabled for acknowledgment.

Actual interrupt request acknowledgment is controlled by the interrupt enable flag (IE).

Carry flag (CY)

This flag stores an overflow or underflow upon add/subtract instruction execution. It stores the shift-out value

upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction

(3) Stack pointer (SP)

This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high-speed

RAM area (FB00H to FEFFH) can be set as the stack area.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
UPD780101MC-047-5A4-E1-A	制造商:Renesas Electronics Corporation 功能描述:
UPD780102MC-082-5A4-A	制造商:Renesas Electronics Corporation 功能描述:
UPD780102MC-083-5A4-A	制造商:Renesas Electronics Corporation 功能描述:
UPD780134GK-424-9ET-E3-A	制造商:Renesas Electronics Corporation 功能描述:
UPD78014GC-765-AB8	制造商:NEC Electronics Corporation 功能描述:

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