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CHAPTER 13 A/D CONVERTER
User
’
s Manual U14260EJ3V1UD
(7) Interrupt request flag (ADIF0)
The interrupt request flag (ADIF0) is not cleared even if analog input channel specification register 0 (ADS0) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF0 for the
pre-change analog input may be set just before the ADS0 rewrite. Caution is therefore required since, at this
time, when ADIF0 is read immediately just after the ADS0 rewrite, ADIF0 is set despite the fact that the A/D
conversion for the post-change analog input has not finished.
When A/D conversion is restarted after it is stopped, clear ADIF0 before restart.
Figure 13-17. A/D Conversion End Interrupt Request Generation Timing
Remarks 1.
n = 0, 1, ......, 7
2.
m = 0, 1, ......, 7
(8) Conversion results just after A/D conversion start
If bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is set to 1 without setting bit 0 (ADCE0) to 1, the
A/D conversion value immediately after A/D conversion has been started may not satisfy the rated value. Take
measures such as polling the A/D conversion end interrupt request (INTAD0) and removing the first conversion
results.
The same may apply if ADCS0 is set to 1 without a lapse of a wait time of 14
μ
s (MIN.) after ADCE0 has been
set to 1. Make sure that the specified wait time elapses.
(9) A/D conversion result register 0 (ADCR0) read operation
When A/D converter mode register 0 (ADM0) and analog input channel specification register 0 (ADS0) are written,
the contents of ADCR0 may become undefined. Read the conversion result following conversion completion
before writing to ADM0 and ADS0. Using a timing other than the above may cause an incorrect conversion result
to be read.
ADM0 rewrite
(start of ANIn conversion)
ADIF is set but ANIm
conversion has not finished.
A/D conversion
ADCR0
ADIF0
ANIn
ANIn
ANIm
ANIm
ANIn
Undefined
ANIm
ANIm
ADS0 rewrite
(start of ANIm conversion)