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CHAPTER 11 WATCHDOG TIMER
User
’
s Manual U14260EJ3V1UD
11.4.2 Interval timer operation
The watchdog timer operates as an interval timer that generates interrupt requests repeatedly at an interval of the
preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0.
The interval time of the interval timer is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock
select register (WDCS). When bit 7 (RUN) of WDTM is set to 1, the watchdog timer operates as an interval timer.
When the watchdog timer operates as an interval timer, the interrupt mask flag (WDTMK) and priority specification
flag (WDTPR) are validated and the maskable interrupt request (INTWDT) can be generated. Among the maskable
interrupts, INTWDT has the highest priority at default.
The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set RUN to 1 before
the STOP mode is set, clear the interval timer and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (this selects the watchdog timer mode), the interval
timer mode is not set unless RESET is input.
2. The interval time just after setting WDTM may be shorter than the set time by up to 2
8
/f
X
seconds.
3. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation
is stopped.
Table 11-3. Interval Timer Interval Time
Interval Time
When Operated at
f
X
= 8.38 MHz
When Operated at
f
X
= 12 MHz
Note
2
12
/f
X
488
μ
s
341
μ
s
2
13
/f
X
977
μ
s
682
μ
s
2
14
/f
X
1.95 ms
1.36 ms
2
15
/f
X
3.91 ms
2.73 ms
2
16
/f
X
7.82 ms
5.46 ms
2
17
/f
X
15.6 ms
10.9 ms
2
18
/f
X
31.2 ms
21.8 ms
2
20
/f
X
125 ms
87.3 ms
Note
Expanded-specification products of
μ
PD780078 Subseries only.
Remark
f
X
: Main system clock oscillation frequency