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CHAPTER 7 CLOCK GENERATOR
User
’
s Manual U14260EJ3V1UD
7.6.2 System clock and CPU clock switching procedure
This section describes procedure for switching between the system clock and CPU clock.
Figure 7-9. System Clock and CPU Clock Switching
<1>
The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
by setting the RESET signal to high level, the main system clock starts oscillation. At this time, the oscillation
stabilization time (2
17
/f
X
) is secured automatically.
After that, the CPU starts executing instructions at the minimum speed of the main system clock (3.81
μ
s @
8.38 MHz operation).
<2>
After the lapse of sufficient time for the V
DD
voltage to increase to enable operation at maximum speeds, PCC
is rewritten and maximum-speed operation is carried out.
<3>
Upon detection of a decrease of the V
DD
voltage due to an interrupt request signal, the main system clock is
switched to the subsystem clock (which must be in an oscillation stable state).
<4>
Upon detection of V
DD
voltage reset due to an interrupt, 0 is set to the MCC and oscillation of the main system
clock is started. After the lapse of the time required for stabilization of oscillation, PCC is rewritten and the
maximum-speed operation is resumed.
Caution
When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
System clock
CPU clock
Interrupt request signal
RESET
V
DD
f
X
f
X
f
XT
f
X
Lowest-
speed
operation
Highest-
speed
operation
Subsystem
clock
operation
High-speed
operation
Wait (15.6 ms: @8.38 MHz operation)
Internal reset operation