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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51
User
’
s Manual U14260EJ3V1UD
9.2 Configuration of 8-Bit Timer/Event Counters 50, 51
8-bit timer/event counters 50, 51 consist of the following hardware.
Table 9-1. Configuration of 8-Bit Timer/Event Counters 50, 51
Item
Configuration
Timer counter
8-bit timer counter 5n (TM5n)
Register
8-bit timer compare register 5n (CR5n)
Timer input
TI5n
Timer output
TO5n
Control registers
Timer clock select register 5n (TCL5n)
8-bit timer mode control register 5n (TMC5n)
Port mode register 7 (PM7)
Port register 7 (P7)
(1) 8-bit timer counter 5n (TM5n: n = 0, 1)
TM5n is an 8-bit read-only register that counts the count pulses.
The counter is incremented in synchronization with the rising edge of the count clock.
Figure 9-3. Format of 8-Bit Timer Counter 5n (TM5n)
When TM50 and TM51 can be connected in cascade and used as a 16-bit timer, they can be read by a 16-bit
memory manipulation instruction. However, since they are connected by an internal 8-bit bus, TM50 and TM51
are read separately twice in that order. Thus, take reading during the count change into consideration and
compare them by reading twice.
When the count value is read during operation, the count clock input is temporarily stopped
Note
, and then the count
value is read.
In the following situations, count value is set to 00H.
<1>
RESET input
<2>
When TCE5n is cleared
<3>
When TM5n and CR5n match in the clear & start mode entered on a match between TM5n and CR5n.
Note
An error may occur in the count. Select a count clock that has a high/low level longer than two cycles
of the CPU clock.
Caution
In cascade connection mode, the count value is reset to 0000H when TCE50 of the lowest timer
is cleared.
Remark
n = 0, 1
Symbol
TM5n
(n = 0, 1)
Address: FF12H (TM50), FF13H (TM51) After reset: 00H R