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CHAPTER 18 SERIAL INTERFACE IIC0 (
μ
PD780078Y SUBSERIES ONLY)
User
’
s Manual U14260EJ3V1UD
Figure 18-5. Format of IIC Control Register 0 (IICC0) (1/4)
Address: FFA8H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
IICC0
IICE0
LREL0
WREL0
SPIE0
WTIM0
ACKE0
STT0
SPT0
IICE0
I
2
C operation enable
0
Stop operation. Reset IIC status register 0 (IICS0). Stop internal operation.
1
Enable operation.
Condition for clearing (IICE0 = 0)
Condition for setting (IICE0 = 1)
Cleared by instruction
When RESET is input
Set by instruction
LREL0
Exit from communications
0
Normal operation
1
This exits from the current communications operation and sets standby mode. This setting is
automatically cleared after being executed. Its uses include cases in which a locally irrelevant
extension code has been received.
The SCL0 and SDA0 lines go into the high impedance state.
The following flags of IIC status register 0 (IICS0) and IIC control register 0 (IICC0) are cleared.
STD0
ACKD0
TRC0
COI0
EXC0
MSTS0
STT0
SPT0
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
After a stop condition is detected, restart is in master mode.
An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0)
Note
Condition for setting (LREL0 = 1)
Automatically cleared after execution
When RESET is input
Set by instruction
WREL0
Cancel wait
0
Do not cancel wait.
1
Cancel wait. This setting is automatically cleared after wait is canceled.
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status
(TRC0 = 1), the SDA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0)
Note
Condition for setting (WREL0 = 1)
Automatically cleared after execution
When RESET is input
Set by instruction
SPIE0
Enable/disable generation of interrupt request when stop condition is detected
0
Disable
1
Enable
Condition for clearing (SPIE0 = 0)
Note
Condition for setting (SPIE0 = 1)
Cleared by instruction
When RESET is input
Set by instruction
Note
This flag
’
s signal is invalid when IICE0 = 0.