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168
CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01
User
’
s Manual U14260EJ3V1UD
(3) Pulse width measurement with free-running counter and two capture registers
When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to measure the pulse width
of the signal input to the TI00n pin.
When the rising or falling edge specified by bits 4 and 5 (ES00n and ES01n) of prescaler mode register 0n
(PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n
(CR01n) and an interrupt request signal (INTTM01n) is set.
Also, when the inverse edge to that of the capture operation to CR01n is input, the value of TM0n is taken into
16-bit timer capture/compare register 00n (CR00n).
Sampling is performed with the count clock cycle selected by prescaler mode register 0n (PRM0n), and a capture
operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise with a
short pulse width.
Caution
If the valid edge of the TI00n pin is specified to be both the rising and falling edges, 16-bit timer
capture/compare register 00n (CR00n) cannot perform the capture operation.
Figure 8-28. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers (with Rising Edge Specified)
(a) 16-bit timer mode control register 0n (TMC0n)
(b) Capture/compare control register 0n (CRC0n)
(c) Prescaler mode register 0n (PRM0n)
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
n = 0, 1
7
0
6
0
5
0
4
0
TMC0n3
0
TMC0n2
1
1
0
OVF0n
0
TMC0n
Free-running mode
7
0
6
0
5
0
4
0
3
0
CRC02n
1
CRC01n
1
CRC00n
1
CRC0n
CR00n used as capture register
Captures to CR00n at edge reverse
to valid edge of TI00n pin.
CR01n used as capture register
ES11n
0/1
ES10n
0/1
ES01n
0
ES00n
1
3
0
2
0
PRM01n
0/1
PRM00n
0/1
PRM0n
Selects count clock (setting
“
11
”
is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting
“
10
”
is prohibited.)