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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51
User
’
s Manual U14260EJ3V1UD
9.4.5 Interval timer (16-bit) operations
When bit 4 (TMC514) of 8-bit timer mode control register 51 (TMC51) is set to 1, the 16-bit resolution timer/counter
mode is entered.
The 8-bit timer/event counter operates as an interval timer that generates interrupt requests repeatedly at intervals
of the count value preset to the 8-bit timer compare registers (CR50, CR51).
Setting
<1>
Set each register.
TCL50:
Select count clock for TM50.
Cascade-connected TM51 need not be selected.
Compare value (each value can be set to 00H to FFH)
TMC50, TMC51: Select the clear & start mode entered on a match between TM50 and CR50 (TM51 and
CR51).
TM50
→
TMC50 = 0000
×××
0B
×
: don
’
t care
TM51
→
TMC51 = 0001
×××
0B
×
: don
’
t care
When TMC51 is set to TCE51 = 1 and then TMC50 is set to TCE50 = 1, the count operation starts.
When the values of TM50 and CR50 of the cascade-connected timer match, INTTM50 of TM50 is generated
(TM50 and TM51 are cleared to 00H).
INTTM5n is generated repeatedly at the same interval.
CR50, CR51:
<2>
<3>
<4>
Cautions 1. Stop the timer operation without fail before setting the compare registers (CR50, CR51).
2. INTTM51 of TM51 is generated when the TM51 count value matches CR51, even if cascade
connection is used. Be sure to mask TM51 to disable interrupts.
3. Set TCE50 and TCE51 in order of TM51 then TM50.
4. Count restart/stop can only be controlled by setting TCE50 of TM50 to 1/0.
Figure 9-15 shows an example of 16-bit resolution cascade connection mode timing.
Figure 9-15. 16-Bit Resolution Cascade Connection Mode
Count clock
TM50
TM51
CR50
CR51
TCE50
TCE51
INTTM50
Operation enable
Count start
Interval time
00H
01H
N
N+1
FFH 00H
FFH 00H
FFH 00H 01H
N
00H 01H
A
00H
00H
01H
02H
M
–
1
M
00H
B
00H
N
M
Interrupt request
generation,
counter clear
Operation
stop