參數(shù)資料
型號(hào)： TMS320SP5410AZGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 91/100頁
文件大小： 913K
代理商： TMS320SP5410AZGU12
www.ti.com
5.15.2
HPI16 Mode
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 5-34 and Table 5-35 assume testing over recommended operating conditions and P = 0.5 *
processor clock (see Figure 5-32 through Figure 5-34). In the following tables, DS refers to the logical OR
of HCS, HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These
timings are shown assuming that HDS is the signal controlling the transfer. See the
TMS320C54x DSP
Reference Set,Volume 5: Enhanced Peripherals
(literature number SPRU302) for addition information.
Table 5-34. HPI16 Mode Timing Requirements
5410A-120
5410A-160
MIN
6
5
5
–(4P – 6)
1
30
10
10P + 30
10P + 10
16P + 30
16P + 10
24P + 30
24P + 10
8
2
UNIT
MAX
t
su(HBV-DSL)
t
h(DSL-HBV)
t
su(HAV-DSH)
t
su(HAV-DSL)
t
h(DSH-HAV)
tw(DSL)
t
w(DSH)
Setup time, HR/W valid before DS falling edge
Hold time, HR/W valid after DS falling edge
Setup time, address valid before DS rising edge (write)
Setup time, address valid before DS falling edge (read)
Hold time, address valid after DS rising edge
Pulse duration, DS low
Pulse duration, DS high
ns
ns
ns
ns
ns
ns
ns
Reads
Writes
Reads
Writes
Reads
Writes
Memory accesses with no DMA
activity.
Cycle time, DS rising edge to next
DS rising edge
Memory accesses with 16-bit DMA
activity.
t
c(DSH-DSH)
ns
Memory accesses with 32-bit DMA
activity.
t
su(HDV-DSH)W
t
h(DSH-HDV)W
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge, write
ns
ns
91
Electrical Specifications
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