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TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
4
Support
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 53
4.1
Documentation Support
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 53
4.2
Device and Development-Support Tool Nomenclature
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 54
Electrical Specifications
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 55
5.1
Absolute Maximum Ratings
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 55
5.2
Recommended Operating Conditions
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 55
5.3
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
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 56
5.4
Test Load Circuit
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 57
5.5
Timing Parameter Symbology
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 57
5.6
Internal Oscillator With External Crystal
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 58
5.7
Clock Options
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 59
5.7.1
Divide-By-Two and Divide-By-Four Clock Options
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 59
5.7.2
Multiply-By-N Clock Option (PLL Enabled)
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 61
5.8
Memory and Parallel I/O Interface Timing
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 62
5.8.1
Memory Read
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 62
5.8.2
Memory Write
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 65
5.8.3
I/O Read
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 67
5.8.4
I/O Write
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 69
5.9
Ready Timing for Externally Generated Wait States
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 70
5.10
HOLD and HOLDA Timings
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 73
5.11
Reset, BIO, Interrupt, and MP/MC Timings
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 75
5.12
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
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 77
5.13
External Flag (XF) and TOUT Timings
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 78
5.14
Multichannel Buffered Serial Port (McBSP) Timing
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 79
5.14.1
McBSP Transmit and Receive Timings
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 79
5.14.2
McBSP General-Purpose I/O Timing
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 82
5.14.3
McBSP as SPI Master or Slave Timing
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 83
5.15
Host-Port Interface Timing
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 87
5.15.1
HPI8 Mode
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 87
5.15.2
HPI16 Mode
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 91
Mechanical Data
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 95
6.1
Package Thermal Resistance Characteristics
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 95
5
6
4
Contents