參數(shù)資料
型號： TMS320SP5410AZGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 29/100頁
文件大?。?/td> 913K
代理商： TMS320SP5410AZGU12
www.ti.com
3.4
Multichannel Buffered Serial Ports (McBSPs)
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
The 5410A device provides high-speed, full-duplex serial ports that allow direct interface to other
C54x/LC54x devices, codecs, and other devices in a system. There are three multichannel buffered serial
ports (McBSPs) on board (three per subsystem).
The McBSP provides:
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
Direct interface to:
–
T1/E1 framers
–
MVIP switching-compatible and ST-BUS compliant devices
–
IOM-2 compliant device
–
AC97-compliant device
–
Serial peripheral interface (SPI)
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits
μ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The 5410A McBSPs have been enhanced to provide more flexibility in the choice of the sample rate
generator input clock source. On previous TMS320C5000 DSP platform devices, the McBSP sample
rate input clock can be driven from one of two possible choices: the internal CPU clock , or the external
CLKS pin. However, most C5000 DSP devices have only the internal CPU clock as a possible source
because the CLKS pin is not implemented on most device packages.
To accommodate applications that require an external reference clock for the sample rate generator, the
5410A McBSPs allow either the receive clock pin (BCLKR) or the transmit clock pin (BCLKX) to be
configured as the input clock to the sample rate generator. This enhancement is enabled through two
register bits: pin control register (PCR) bit 7 - enhanced sample clock mode (SCLKME), and sample rate
generator register 2 (SRGR2) bit 13 - McBSP sample rate generator clock mode (CLKSM). SCLKME is an
addition to the PCR contained in the McBSPs on previous C5000 devices. The new bit layout of the PCR
is shown in Figure 3-10. For a description of the remaining bits, see
TMS320C54x DSP Reference Set,
Volume 5: Enhanced Peripherals
(literature number SPRU302).
15
14
13
12
11
10
9
8
Reserved
XIOEN
RIOEN
FSXM
FSRM
CLKXM
CLKRM
R, +0
R/W,+0
R/W,+0
R/W,+0
R/W,+0
R/W,+0
R/W,+0
7
6
5
4
3
2
1
0
SCLKME
CLKS_STAT
DX_STAT
DR_STAT
FSXP
FSRP
CLKXP
CLKRP
R/W, +0
LEGEND: R = Read, W = Write, n = value at reset
R, +0
R, +0
R, +0
R/W,+0
R/W,+0
R/W,+0
R/W,+0
Figure 3-10. Pin Control Register (PCR)
Functional Overview
29
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