參數(shù)資料
型號: TMS320SP5410AZGU12
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processor
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 33/100頁
文件大小: 913K
代理商: TMS320SP5410AZGU12
www.ti.com
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock
mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock
module. Note that upon reset, the CLKMD register is initialized with a predetermined value dependent only
upon the state of the CLKMD1 - CLKMD3 pins. For more programming information, see the
TMS320C54x
DSP Reference Set, Volume 1: CPU and Peripherals
(literature number SPRU131). The CLKMD pin
configured clock options are shown in Table 3-10.
Table 3-10. Clock Mode Settings at Reset
CLKMD1
0
0
0
1
1
1
1
0
CLKMD2
0
0
1
0
1
1
0
1
CLKMD3
0
1
0
0
0
1
1
1
CLKMD RESET VALUE
0000h
9007h
4007h
1007h
F007h
0000h
F000h
CLOCK MODE
(1)
1/2 (PLL and Oscillator disabled)
PLL x 10 (Oscillator enabled)
PLL x 5 (Oscillator enabled)
PLL x 2(Oscillator enabled)
PLL x 1 (Oscillator enabled)
1/2 (PLL disabled, Oscillator enabled)
1/4 (PLL disabled, Oscillator enabled)
Reserved (Bypass mode)
(1)
The external CLKMD1-CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the
clock generation mode can be reconfigured by writing to the internal clock mode register in software. However, the oscillator
enable/disable selection is performed independently of the state of RS; therefore, if CLKMD1-CLKMD3 are changed following reset, the
oscillator enable/disable selection may change, but other aspects of the clock generation mode will not.
Functional Overview
33
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