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參數(shù)資料
| 型號： | TMS320SP5410AZGU12 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor |
| 中文描述： | 定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 70/100頁 |
| 文件大?。?/td> | 913K |
| 代理商： | TMS320SP5410AZGU12 |
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5.9
Ready Timing for Externally Generated Wait States
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 5-13 and Table 5-14 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 5-10, Figure 5-11, Figure 5-12, and Figure 5-13).
Table 5-13. Ready Timing Requirements for Externally Generated Wait States
(1)
5410A-120
5410A-160
MIN
7
0
UNIT
MAX
t
su(RDY)
t
h(RDY)
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
(1)
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states
by READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software
wait states.
(2)
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low
(2)
Hold time, READY after MSTRB low
(2)
Valid time, READY after IOSTRB low
(2)
Hold time, READY after IOSTRB low
(2)
ns
ns
ns
ns
ns
ns
4H – 4
4H
4H – 4
4H
Table 5-14. Ready Switching Characteristics for Externally Generated Wait States
(1)
5410A-120
5410A-160
MIN
– 1
– 1
PARAMETER
UNIT
MAX
t
d(MSCL)
t
d(MSCH)
(1)
Delay time, CLKOUT low to MSC low
Delay time, CLKOUT low to MSC high
4
4
ns
ns
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states
by READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software
wait states.
Electrical Specifications
70
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