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| 型號： | TMS320SP5410AZGU12 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor |
| 中文描述： | 定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 88/100頁 |
| 文件大?。?/td> | 913K |
| 代理商： | TMS320SP5410AZGU12 |
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TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 5-33. HPI8 Mode Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
MAX
10
t
en(DSL-HD)
Enable time, HD driven from DS low
0
ns
Case 1a: Memory accesses when DMAC is active in
16-bit mode and t
w(DSH)
< I8H
(1)
Case 1b: Memory accesses when DMAC is active in
32-bit mode and t
w(DSH)
≥
I8H
(1)
Case 1c: Memory accesses when DMAC is active in
16-bit mode and t
w(DSH)
≥
I8H
(1)
Case 1d: Memory accesses when DMAC is active in
32-bit mode and t
w(DSH)
≥
I8H
(1)
Case 2a: Memory accesses when DMAC is inactive
and t
w(DSH)
< 10H
(1)
Case 2b: Memory accesses when DMAC is inactive
and t
w(DSH)
≥
10H
(1)
Case 3: Register accesses
18P+10–t
w(DSH)
36P+10–t
w(DSH)
10
Delay time, DS low to HD
valid for first byte of an
HPI read
t
d(DSL-HDV1)
ns
10
10P+10–t
w(DSH)
10
10
10
t
d(DSL-HDV2)
t
h(DSH-HDV)R
t
v(HYH-HDV)
t
d(DSH-HYL)
Delay time, DS low to HD valid for second byte of an HPI read
Hold time, HD valid after DS high, for a HPI read
Valid time, HD valid after HRDY high
Delay time, DS high to HRDY low
(2)
Case 1a: Memory accesses when DMAC is active in
16-bit mode
(1)
Case 1b: Memory accesses when DMAC is active in
Delay time, DS high to
32-bit mode
(1)
HRDY high
(2)
Case 2: Memory accesses when DMAC is inactive
(1)
Case 3: Write accesses to HPIC register
(3)
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output
ns
ns
ns
ns
0
2
8
18P+6
36P+6
t
d(DSH-HYH)
ns
10P+6
6P+6
6
9
6
t
d(HCS-HRDY)
t
d(COH-HYH)
t
d(COH-HTX)
ns
ns
ns
t
d(COH-GPIO)
5
ns
(1)
DMAC stands for direct memory access controller (DMAC). The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access
times are affected by DMAC activity.
The HRDY output is always high when the HCS input is high, regardless of DS timings.
This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronously, and do not cause HRDY to be deasserted.
(2)
(3)
Electrical Specifications
88
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