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參數(shù)資料
| 型號： | TMS320SP5410AZGU12 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor |
| 中文描述： | 定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 38/100頁 |
| 文件大?。?/td> | 913K |
| 代理商： | TMS320SP5410AZGU12 |
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www.ti.com
3.8.3
DMPREC Issue
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
These new bit fields were created to allow the user to define the space-select for the DMA
(internal/external). The functions of the DLAXS and SLAXS bits are as follows:
DLAXS(DMMCRn[5]) Destination
0 = No external access (default internal)
1 = External access
0 = No external access (default internal)
1 = External access
SLAXS(DMMCRn[11]) Source
Table 3-11 lists the DMD bit values and their corresponding destination space.
Table 3-11. DMD Section of the DMMCRn Register
DMD
00
01
10
11
DESTINATION SPACE
PS
DS
I/O
Reserved
For the CPU external access, software can configure the memory cells to reside inside or outside the
program address map. When the cells are mapped into program space, the device automatically accesses
them when their addresses are within bounds. When the address generation logic generates an address
outside its bounds, the device automatically generates an external access.
When updating the DE bits of the DMPREC register while one or more DMA channel transfers are in
progress, it is possible for the write to the DMPREC to cause an additional transfer on one of the active
channels.
The problem occurs when an active channel completes a transfer at the same time that the user updates
the DMPREC register. When the transfer completes, the DMA logic attempts to clear the DE bit
corresponding to the complete channel transfer, but the register is instead updated with the CPU write
(usually an ORM instruction) which can set the bit and cause an additional transfer on the channel. See
the
TMS320VC5410A Digital Signal Processor Silicon Errata
(literature number SPRZ187) for further
clarification.
38
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