參數(shù)資料
型號： TMS320SP5410AZGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 31/100頁
文件大?。?/td> 913K
代理商： TMS320SP5410AZGU12
www.ti.com
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Figure 3-12. Multichannel Control Register 1x (MCR1x)
In the second mode, with RMCME = 1 and XMCME = 1, the McBSPs have 128 channel selection
capability. Twelve new registers (RCERCx-RCERHx and XCERCx-XCERHx) are used to enable the
128 channel selection. The subaddresses of the new registers are shown in Table 3-19. These new
registers, functionally equivalent to the RCERA0-RCERB1 and XCERA0-XCERB1 registers in the
5420, are used to enable/disable the transmit and receive of additional channel partitions (C,D,E,F,G,
and H) in the128 channel stream. For example, XCERH1 is the transmit enable for channel partition H
(channels 112 to 127) of MCBSP1 for each DSP subsystem. See Figure 3-13, Table 3-8, Figure 3-14,
and Table 3-9 for bit layout and function of the receive and transmit registers .
15
14
13
12
11
10
9
8
RCERyz15
RCERyz14
RCERyz13
RCERyz12
RCERyz11
RCERyz10
RCERyz9
RCERyz8
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
7
6
5
4
3
2
1
0
RCERyz7
RCERyz6
RCERyz5
RCERyz4
RCERyz3
RCERyz2
RCERyz1
RCERyz0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
LEGEND: R = Read, W = Write, n = value at reset; y = partition A, B, C, D, E, F, G, or H; z = McBSP0,1, or 2
Figure 3-13. Receive Channel Enable Registers Bit Layout for Partitions A to H
Table 3-8. Receive Channel Enable Registers for Partitions A to H Field Descriptions
BIT
FIELD
VALUE
DESCRIPTION
Receive Channel Enable Register
Disables reception of
n
th channel in partition y.
Enables reception of
n
th channel in partition y.
15-0
RCERyz(15:0)
0
1
15
14
13
12
11
10
9
8
XCERyz15
XCERyz14
XCERyz13
XCERyz12
XCERyz11
XCERyz10
XCERyz9
XCERyz8
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
7
6
5
4
3
2
1
0
XCERyz7
XCERyz6
XCERyz5
XCERyz4
XCERyz3
XCERyz2
XCERyz1
XCERyz0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
LEGEND: R = Read, W = Write, n = value at reset; y = partition A, B, C, D, E, F, G, or H; z = McBSP0,1, or 2
Figure 3-14. Transmit Channel Enable Registers Bit Layout for Partitions A to H
Table 3-9. Transmit Channel Enable Registers for Partitions A to H Field Descriptions
BIT
FIELD
VALUE
DESCRIPTION
Transmit Channel Enable Register
Disables transmit of
n
th channel in partition y.
Enables transmit of
n
th channel in partition y.
15-0
XCERyz(15:0)
0
1
Functional Overview
31
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