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參數(shù)資料
| 型號： | TMS320SP5410AZGU12 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor |
| 中文描述： | 定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 62/100頁 |
| 文件大小： | 913K |
| 代理商： | TMS320SP5410AZGU12 |
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t
c(CO)
t
c(CI)
t
w(COH)
t
f(CO)
t
r(CO)
t
f(CI)
X2/CLKIN
CLKOUT
(A)
t
d(CI-CO)
t
w(COL)
t
r(CI)
tp
Unstable
t
w(CIH)
t
w(CIL)
5.8
Memory and Parallel I/O Interface Timing
5.8.1
Memory Read
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
A.
The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as
00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5-4. Multiply-By-One Clock Timing
Address delay times are longer for cycles immediatly following a HOLD operation. All timings related to
the address bus have been seperated in to two cases; one showing normal operation and the other
showing the delays related to the HOLD operation.
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR. Table 5-7 and Table 5-8 assume testing over recommended operating
conditions with MSTRB = 0 and H = 0.5t
c(CO)
(see Figure 5-5 and Figure 5-6).
Table 5-7. Memory Read Timing Requirements
5410A-120
5410A-160
MIN
UNIT
MAX
For accesses not immediately following a
HOLD operation
For a read accesses immediately following a
HOLD operation
4H–9
ns
Access time, read data access from address
valid, first read access
(1)
t
a(A)M1
4H–11
ns
t
a(A)M2
t
su(D)R
t
h(D)R
(1)
Access time, read data access from address valid, consecutive read accesses
(1)
Setup time, read data valid before CLKOUT low
Hold time, read data valid after CLKOUT low
2H–9
ns
ns
ns
7
0
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Table 5-8. Memory Read Switching Characteristics
5410A-120
5410A-160
MIN
PARAMETER
UNIT
MAX
For accesses not immediately following a
HOLD operation
For a read accesses immediately following a
HOLD operation
– 1
4
ns
t
d(CLKL-A)
Delay time, CLKOUT low to address valid
(1)
– 1
6
ns
t
d(CLKL-MSL)
t
d(CLKL-MSH)
(1)
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to MSTRB high
– 1
– 1
4
4
ns
ns
Electrical Specifications
62
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