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參數(shù)資料
| 型號(hào)： | TMS320SP5410AZGU12 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Fixed-Point Digital Signal Processor |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 69/100頁(yè) |
| 文件大?。?/td> | 913K |
| 代理商： | TMS320SP5410AZGU12 |
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5.8.4
I/O Write
t
d(CLKL-D)W
CLKOUT
D[15:0]
IOSTRB
t
d(CLKL-D)W
t
su(D)IOSH
t
d(CLKL-IOSH)
t
h(D)IOSH
t
su(A)IOS
L
t
w(SL)IOS
t
d(CLKL-IOSL
)
t
d(CLKL-A)
A[22:0]
(A)
R/W
(A)
IS
(A)
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 5-12 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t
c(CO)
(see
Figure 5-9).
Table 5-12. I/O Write Switching Characteristics
5410A-120
5410A-160
MIN
PARAMETER
UNIT
MAX
For accesses not immediately following a
HOLD operation
For a read accesses immediately following a
HOLD operation
For accesses not immediately following a
HOLD operation
For a read accesses immediately following a
HOLD operation
– 1
4
ns
Delay time, CLKOUT low to address
valid
(1)
t
d(CLKL-A)
– 1
6
ns
2H – 3
ns
Setup time, address valid before IOSTRB
low
(1)
t
su(A)IOSL
2H – 5
ns
t
d(CLKL-D)W
t
su(D)IOSH
t
h(D)IOSH
t
d(CLKL-IOSL)
t
w(SL)IOS
t
d(CLKL-IOSH)
(1)
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
Delay time, CLKOUT low to write data valid
Setup time, data valid before IOSTRB high
Hold time, data valid after IOSTRB high
Delay time, CLKOUT low to IOSTRB low
Pulse duration, IOSTRB low
Delay time, CLKOUT low to IOSTRB high
– 1
4
ns
ns
ns
ns
ns
ns
2H – 5
2H – 5
– 1
2H – 2
– 1
2H + 6
2H + 6
4
4
A.
NOTE: Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-9. Parallel I/O Port Write (IOSTRB = 0)
Electrical Specifications
69
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