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參數(shù)資料
| 型號： | TMS320SP5410AZGU12 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor |
| 中文描述： | 定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 13/100頁 |
| 文件大?。?/td> | 913K |
| 代理商： | TMS320SP5410AZGU12 |
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2.3
Signal Descriptions
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 2-2 lists each signal, function, and operating mode(s) grouped by function. See Section Section 2.2
for exact pin locations based on package type.
Table 2-2. Signal Descriptions
TERMINAL
NAME
I/O
(1)
DESCRIPTION
DATA SIGNALS
A22 (MSB)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (LSB)
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
I/O/Z
(2)(3)
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen
LSB lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB
lines, A16 to A22, address external program space memory. A22-A0 is placed in the high-impedance state
in the hold mode. A22-A0 also goes into the high-impedance state when OFF is low.
A16-A0 are inputs in HPI16 mode. These pins can be used to address internal memory via the host-port
interface (HPI) when the HPI16 pin is high. These pins also have Schmitt trigger inputs.
The address bus has a bus holder feature that eliminates passive components and the power dissipation
associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes
into a high-impedance state.
I/O/Z
(2)(3)
Parallel data bus D15 (MSB) through D0 (LSB). D15-D0 is multiplexed to transfer data between the core
CPU and external data/program memory or I/O devices or HPI in HPI16 mode (when HPI16 pin is high).
D15-D0 is placed in the high-impedance state when not outputting data or when RS or HOLD is asserted.
D15-D0 also goes into the high-impedance state when OFF is low. These pins also have Schmitt trigger
inputs.
The data bus has a bus holder feature that eliminates passive components and the power dissipation
associated with them. The bus holder keeps the data bus at the previous logic level when the bus goes
into the high-impedance state. The bus holders on the data bus can be enabled/disabled under software
control.
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is
fetching the interrupt vector location designated by A15-A0. IACK also goes into the high-impedance state
when OFF is low.
IACK
O/Z
INT0
(2)
INT1
(2)
INT2
(2)
INT3
(2)
External user interrupt inputs. INT0-INT3 are maskable and are prioritized by the interrupt mask register
(IMR) and the interrupt mode bit. INT0 -INT3 can be polled and reset by way of the interrupt flag register
(IFR).
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR.
When NMI is activated, the processor traps to the appropriate vector location.
Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program
counter to 0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program
memory. RS affects various registers and status bits.
NMI
(2)
I
RS
(2)
I
(1)
(2)
(3)
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
Introduction
13
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