參數(shù)資料
型號(hào)： TMS320SP5410AZGU12
廠(chǎng)商： Texas Instruments, Inc.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 80/100頁(yè)
文件大?。?/td> 913K
代理商： TMS320SP5410AZGU12
www.ti.com
(n-2)
Bit (n-1)
(n-3)
(n-2)
Bit (n-1)
(n-4)
(n-3)
(n-2)
Bit (n-1)
t
h(BCKRL-BDRV)
t
su(BDRV-BCKRL)
t
h(BCKRL-BDRV)
t
su(BDRV-BCKRL)
t
su(BDRV-BCKRL)
t
h(BCKRL-BDRV)
t
h(BCKRL-BFRH)
t
d(BCKRH-BFRV)
t
d(BCKRH-BFRV)
t
r(BCKRX)
t
r(BCKRX)
t
w(BCKRXL)
t
c(BCKRX)
t
w(BCKRXH)
(RDATDLY=10b)
BDR
(RDATDLY=01b)
BDR
(RDATDLY=00b)
BDR
BFSR (ext)
BFSR (int)
BCLKR
t
su(BFRH-BCKRL)
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 5-21. McBSP Transmit and Receive Switching Characteristics
(1)
5410A-120
5410A-160
MIN
4P
(2)
D – 1
(3)
C – 1
(3)
– 3
0
– 1
2
PARAMETER
UNIT
MAX
t
c(BCKRX)
t
w(BCKRXH)
Cycle time, BCLKR/X
Pulse duration, BCLKR/X high
Pulse duration, BCLKR/X low
BCLKR/X int
BCLKR/X int
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BFSX int
BFSX ext
ns
ns
ns
ns
ns
D + 1
(3)
C + 1
(3)
3
11
5
10
6
10
10
20
7
11
t
w(BCKRXL)
t
d(BCKRH-BFRV)
Delay time, BCLKR high to internal BFSR valid
t
d(BCKXH-BFXV)
Delay time, BCLKX high to internal BFSX valid
ns
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
t
dis(BCKXH-BDXHZ)
ns
– 1
(5)
2
–1
(5)
2
t
d(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
DXENA = 0
(4)
ns
Delay time, BFSX high to BDX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
t
d(BFXH-BDXV)
ns
(1)
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
P = 0.5 * processor clock
T = BCLKRX period = (1 + CLKGDV) * 2P
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
The transmit delay enable (DXENA) feature of the McBSP is not implemented on the TMS320VC5410A.
Minimum delay times also represent minimum output hold times.
(2)
(3)
(4)
(5)
Figure 5-21. McBSP Receive Timings
80
Electrical Specifications
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