參數(shù)資料
型號： TMS320SP5410AZGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 83/100頁
文件大?。?/td> 913K
代理商： TMS320SP5410AZGU12
www.ti.com
5.14.3
McBSP as SPI Master or Slave Timing
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
BCLKX
BFSX
BDX
BDR
t
su(BDRV-BCLXL)
t
d(BCKXH-BDXV)
t
h(BCKXL-BDRV)
t
dis(BFXH-BDXHZ)
t
dis(BCKXL-BDXHZ)
t
h(BCKXL-BFXL)
t
d(BFXL-BDXV)
t
d(BFXL-BCKXH)
LSB
MSB
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 5-24 to Table 5-31 assume testing over recommended operating conditions (see Figure 5-24,
Figure 5-25, Figure 5-26, and Figure 5-27).
Table 5-24. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
(1)
5410A-120
5410A-160
UNIT
MASTER
MIN
12
4
SLAVE
MIN
2 – 6P
(2)
5 + 12P
(2)
MAX
MAX
t
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
(1)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2)
P = 0.5 * processor clock
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
ns
ns
Table 5-25. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
(1)
5410A-120
5410A-160
PARAMETER
UNIT
MASTER
(2)
MIN
T – 3
C – 4
– 4
SLAVE
MAX
T + 4
C + 3
5
MIN
MAX
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
d(BCKXH-BDXV)
Hold time, BFSX low after BCLKX low
(3)
Delay time, BFSX low to BCLKX high
(4)
Delay time, BCLKX high to BDX valid
Disable time, BDX high impedance following last data bit
from BCLKX low
Disable time, BDX high impedance following last data bit
from BFSX high
Delay time, BFSX low to BDX valid
ns
ns
ns
6P + 2
(5)
10P + 17
(5)
t
dis(BCKXL-BDXHZ)
C – 2
C + 3
ns
t
dis(BFXH-BDXHZ)
2P– 4
(5)
6P + 17
(5)
ns
t
d(BFXL-BDXV)
(1)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2)
T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
(3)
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(4)
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the
master clock (BCLKX).
(5)
P = 0.5 * processor clock
4P+ 2
(5)
8P + 17
(5)
ns
Figure 5-24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Electrical Specifications
83
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