參數(shù)資料
型號(hào)： TMS320SP5410AZGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 10/100頁
文件大?。?/td> 913K
代理商： TMS320SP5410AZGU12
www.ti.com
2.1
Description
2.2
Terminal/Pin Assignments
2.2.1
Terminal Assignments for the GGU Package
A
B
D
C
E
F
H
J
L
M
K
N
G
1
2
3
4
5
6
7
8
10
12 11
13
9
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
The TMS320VC5410A fixed-point, digital signal processor (DSP) (hereafter referred to as the 5410A
unless otherwise specified) is based on an advanced modified Harvard architecture that has one program
memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a
high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip
peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction
set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing
a high degree of parallelism. Two read operations and one write operation can be performed in a single
cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture.
In addition, data can be transferred between data and program spaces. Such parallelism supports a
powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single
machine cycle. The 5410A also includes the control mechanisms to manage interrupts, repeated
operations, and function calls.
Figure 2-1 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in
conjunction with Table 2-1 to locate signal names and ball grid numbers. Figure 2-2 provides the pin
assignments for the 144-pin low-profile quad flatpack (LQFP) package.
Figure 2-1. 144-Ball GGU MicroStar BGA (Bottom View)
Table 2-1 lists each signal name and BGA ball number for the 144-pin TMS320VC5410AGGU package.
Table 2-2 lists each terminal name, terminal function, and operating modes for the TMS320VC5410A.
DV
DD
is the power supply for the I/O pins while CV
DD
is the power supply for the core CPU. DV
SS
is the
ground for the I/O pins while CV
SS
is the ground for the core CPU. The DV
SS
and CV
SS
pins can be
connected to a common ground plane in a system.
10
Introduction
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