參數(shù)資料
型號(hào)： TMS320SP5410AZGU12
廠商： Texas Instruments, Inc.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 37/100頁(yè)
文件大?。?/td> 913K
代理商： TMS320SP5410AZGU12
www.ti.com
3.8
DMA Controller
3.8.1
Features
3.8.2
DMA External Access
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
The 5410A direct memory access (DMA) controller transfers data between points in the memory map
without intervention by the CPU. The DMA allows movements of data to and from internal program/data
memory, internal peripherals (such as the McBSPs), or external memory devices to occur in the
background of CPU operation. The DMA has six independent programmable channels, allowing six
different contexts for DMA operation.
The DMA has the following features:
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block
transfers.
The DMA has higher priority than the CPU for both internal and external accesses.
Each channel has independently programmable priorities.
Each channel's source and destination address registers can have configurable indexes through
memory on each read and write transfer, respectively. The address may remain constant, be
post-incremented, be post-decremented, or be adjusted by a programmable value.
Each read or write internal transfer may be initialized by selected events.
On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU.
The DMA can perform double-word internal transfers (a 32-bit transfer of two 16-bit words).
The 5410A DMA supports external accesses to extended program, extended data, and extended I/O
memory. These overlay pages are only visible to the DMA controller. A maximum of two DMA channels
can be used for external memory accesses. The DMA external accesses require a minimum of 8 cycles
for external writes and a minimum of 11 cycles for external reads assuming the XIO02 is in consecutive
mode (CONSEC = 1), wait state is set to two, and CLKOUT is not divided (DIVFCT = 00).
The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of
the external bus, the other will be held-off via wait states until the current transfer is complete. The DMA
takes precedence over XIO requests.
Only two channels are available for external accesses. (One for external reads and one for external
writes.)
Single-word (16-bit) transfers are supported for external accesses.
The DMA does not support transfers from the peripherals to external memory.
The DMA does not support transfers from external memory to the peripherals.
The DMA does not support external-to-external transfers.
The DMA does not support sychronized external transfers.
To allow the DMA access to extended data pages, the SLAXS and DLAXS bits are added to the
DMMCRn register (see Figure 3-18).
15
14
13
12
11
10
8
AUTOINIT
DINM
IMOD
CTMOD
SLAXS
SIND
7
6
5
4
2
1
0
DMS
DLAXS
DIND
DMD
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-18. DMA Transfer Mode Control Register (DMMCRn)
Functional Overview
37
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