參數(shù)資料
型號(hào)： TMS320SP5410AZGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 7/100頁
文件大?。?/td> 913K
代理商： TMS320SP5410AZGU12
www.ti.com
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
List of Tables
2-1
Terminal Assignments
...........................................................................................................
11
Signal Descriptions
...............................................................................................................
13
Standard On-Chip ROM Layout
................................................................................................
19
Processor Mode Status Register (PMST) Field Descriptions
...............................................................
22
Software Wait-State Register (SWWSR) Field Descriptions
................................................................
23
Software Wait-State Control Register (SWCR) Field Descriptions
.........................................................
24
Bank-Switching Control Register (BSCR) Field Descriptions
...............................................................
25
Bus Holder Control Bits
..........................................................................................................
26
Sample Rate Generator Clock Source Selection
.............................................................................
30
Receive Channel Enable Registers for Partitions A to H Field Descriptions
..............................................
31
Transmit Channel Enable Registers for Partitions A to H Field Descriptions
.............................................
31
Clock Mode Settings at Reset
...................................................................................................
33
DMD Section of the DMMCRn Register
........................................................................................
38
DMA Channel Enable Control Register (DMCECTL) Field Descriptions
..................................................
39
DMA Reload Register Selection
................................................................................................
42
DMA Interrupts
....................................................................................................................
43
DMA Synchronization Events
....................................................................................................
44
DMA Channel Interrupt Selection
...............................................................................................
44
CPU Memory-Mapped Registers
................................................................................................
47
Peripheral Memory-Mapped Registers for Each DSP Subsystem
.........................................................
48
McBSP Control Registers and Subaddresses
.................................................................................
49
DMA Subbank Addressed Registers
...........................................................................................
50
Interrupt Locations and Priorities
................................................................................................
52
Input Clock Frequency Characteristics
.........................................................................................
58
Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options
........................................
59
Divide-By-2 and Divide-By-4 Clock Options Timing Requirements
........................................................
59
Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics
....................................................
59
Multiply-By-N Clock Option Timing Requirements
............................................................................
61
Multiply-By-N Clock Option Switching Characteristics
.......................................................................
61
Memory Read Timing Requirements
...........................................................................................
62
Memory Read Switching Characteristics
.......................................................................................
62
Memory Write Switching Characteristics
.......................................................................................
65
I/O Read Timing Requirements
.................................................................................................
67
I/O Read Switching Characteristics
.............................................................................................
67
I/O Write Switching Characteristics
.............................................................................................
69
Ready Timing Requirements for Externally Generated Wait States
.......................................................
70
Ready Switching Characteristics for Externally Generated Wait States
...................................................
70
HOLD and HOLDA Timing Requirements
.....................................................................................
73
HOLD and HOLDA Switching Characteristics
.................................................................................
73
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
List of Tables
7
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