參數(shù)資料
型號(hào)： TMS320SP5410AZGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 15/100頁(yè)
文件大?。?/td> 913K
代理商： TMS320SP5410AZGU12
www.ti.com
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
I/O
(1)
DESCRIPTION
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one
CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),
AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
BCLKR0
(2)
Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input
BCLKR1
(2)
I/O/Z
following reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BCLKR2
(2)
BDR0
BDR1
I
Serial data receive input
BDR2
BFSR0
Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is
BFSR1
I/O/Z
configured as an input following reset. The BFSR pulse initiates the receive data process over BDR.
BFSR2
BCLKX0
(2)
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be
BCLKX1
(2)
I/O/Z
configured as an input or an output, and is configured as an input following reset. BCLKX enters the
BCLKX2
(2)
high-impedance state when OFF goes low.
BDX0
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
BDX1
O/Z
asserted, or when OFF is low.
BDX2
HOST-PORT INTERFACE SIGNALS
BFSX0
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process
BFSX1
I/O/Z
over BDX. BFSX can be configured as an input or an output, and is configured as an input following reset.
BFSX2
BFSX goes into the high-impedance state when OFF is low.
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with
the HPI registers. These pins can also be used as general-purpose I/O pins. HD0-HD7 is placed in the
high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus
HD0-HD7
(2)(3)
I/O/Z
holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is
not being driven by the 5410A, the bus holders keep the pins at the previous logic level. The HPI data bus
holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also
have Schmitt trigger inputs.
Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control
HCNTL0
(4)
I
inputs have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16
HCNTL1
(4)
= 1.
Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup
HBIL
(4)
I
resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 = 1.
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select
HCS
(2) (4)
I
input has an internal pullup resistor that is only enabled when HPIENA = 0.
HDS1
(2) (4)
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The
I
HDS2
(2) (4)
strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0.
Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the
HAS
(2) (4)
I
HPIA register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0.
Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is
HR/W
(4)
I
only enabled when HPIENA = 0.
Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the
HRDY
O/Z
host when the HPI is ready for the next transfer.
Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high.
HINT
O/Z
HINT goes into the high-impedance state when OFF is low. This pin is not used when HPI16 = 1.
HPI module select. HPIENA must be tied to DV
to have HPI selected. If HPIENA is left open or
connected to ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled,
HPIENA
(5)
I
and the HPI data bus has holders set. HPIENA is provided with an internal pulldown resistor that is always
active. HPIENA is sampled when RS goes high and is ignored until RS goes low again.
HPI16 mode selection. This pin must be tied to DV
to enable HPI16 mode. The pin has an internal
HPI16
(5)
I
pulldown resistor which is always active. If HPI16 is left open or driven low, the HPI16 mode is disabled.
SUPPLY PINS
CV
SS
S
Ground. Dedicated ground for the core CPU
TOUT
O/Z
(4)
(5)
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
Introduction
15
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