參數(shù)資料
型號： TMS320SP5410AZGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 30/100頁
文件大小： 913K
代理商： TMS320SP5410AZGU12
www.ti.com
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
The selection of the sample rate generator (SRG) clock input source is made by the combination of the
CLKSM and SCLKME bit values as shown in Table 3-7.
Table 3-7. Sample Rate Generator Clock Source Selection
SCLKME
0
0
1
1
CLKSM
0
1
0
1
SRG CLOCK SOURCE
CLKS (not available as a pin on 5410A)
CPU clock
BCLKR pin
BCLKX pin
When either of the bidirectional pins, BCLKR or BCLKX, is configured as the clock input, its output buffer
is automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured
as the SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG
output by setting the PCR bits (9:8) for CLKXM = 1 and CLKRM = 1. However, the SRG output is only
driven onto the BCLKX pin because the BCLKR output is automatically disabled.
The McBSP supports independent selection of multiple channels for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In
using time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to
save memory and bus bandwidth, multichannel selection allows independent enabling of particular
channels for transmission and reception. Up to a maximum of 128 channels in a bit stream can be
enabled or disabled.
The 5410A McBSPs have two working modes that are selected by setting the RMCME and XMCME bits
in the multichannel control registers (MCR1x and MCR2x, respectively). See Figure 3-11 and Figure 3-12.
For a description of the remaining bits, see
TMS320C54x DSP Reference Set, Volume 5: Enhanced
Peripherals
(literature number SPRU302).
In the first mode, when RMCME = 0 and XMCME = 0, there are two partitions (A and B), with each
containing 16 channels as shown in Figure 3-11 and Figure 3-12. This is compatible with the McBSPs
used in earlier TMS320C54x devices, where only 32-channel selection is enabled (default).
15
10
9
8
Reserved
XMCME
XPBBLK
R, +0
R/W, +0
R/W, +0
7
6
5
4
2
1
0
XPBBLK
XPABLK
XCBLK
XMCM
R/W, +0
LEGEND: R = Read, W = Write, n = value at reset
R/W, +0
R, +0
R, +0
Figure 3-11. Multichannel Control Register 2x (MCR2x)
15
10
9
8
Reserved
RMCME
RPBBLK
R, +0
R/W, +0
R/W, +0
7
6
5
4
2
1
0
RPBBLK
RPABLK
RCBLK
RMCM
R/W, +0
LEGEND: R = Read, W = Write, n = value at reset
R/W, +0
R, +0
R, +0
Functional Overview
30
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