參數(shù)資料
型號(hào)： STLC7545
廠商： 意法半導(dǎo)體
英文描述： Enhanced V.34 BIS Analog Front-End(單片模擬前端)
中文描述： 國(guó)際清算銀行增強(qiáng).34模擬前端（單片模擬前端）
文件頁(yè)數(shù)： 8/53頁(yè)
文件大?。?/td> 378K
代理商： STLC7545
I - PIN DESCRIPTION
(continued)
ReceiveSynchronizationPulseOutput
(RxSYNC)
This pin outputs the synchronization receive reset
pulsewhenasoftresetisappliedtotheSTLC7545.
Combined with RxHSCLK clock it can be used to
externallyprovide any synchronousreceive clock.
ReceiveHighest Clock Output
(RxHSCLK)
This pin outputs the highest synchronous receive
clock to give any external or multiplexing clock
when bit 0 of RxCR1 is set to 0 this output is
disabled.
ReceiveOversamplingClock input
(RxOCLK)
Thisinputcan beconnectedto an externalclockto
provide the chip with the oversampling clock, de-
pendingontheExternalOversamplingMode input
Pin (EOCMODE). In normal mode this pin should
be static (tiedto GND or V
DD
).
ExternalOversamplingClock Mode
(EOCMODE)
Thispinisusedforselectingoneof thetwopossible
oversamplingmodes. When EOCMODE is tied to
GND, all the clock are provided internally (mode
compatiblewith the ST7544).When EOCMODEis
tiedto V
DD
, the oversamplingclocksmust be input
on TxOCLK and RxOCLK pins. The TxHSCLK
(RxHSCLK) and TxSync (RxSync) signals along
withexternal fractionaldivider can be used to pro-
vide the oversampling clocks to the STLC7545.
I.3.3- Synchronous Serial Interfaces
(SSIA,SSIB)(10 pins)
SerialSynchronousInterfaceModeinput
(SSIM)
This input activates one or both serial interfaces.
When SSIM is tied to V
DD
, both A and B ports are
functional:port A (SSIA)is dedicatedto theTrans-
mit channel and port B (SSIB) is dedicated to the
Receivechannel.
When SSIM is tied to GND only port A (SSIA) is
selected.In this case SSIAcarries both Tx and Rx
Signalsand EYE pattern.
Bit Frame Rate Select input
(BFRS)
This input selects one of the two possible bit fre-
quenciesfor theBCLKXandBCLKRclocks.When
BFRSis tiedto V
DD
the BCLKX(BCLKR) frequen-
ciesare equalsto the oversamplingratio(dividerV
Table40)timesthe FSX(FSR)frequencies.When
BFRSis tiedto GND,BCLKX(BCLKR)frequencies
areequal to V/2 timesthe FSX(FSR) frequencies.
FrameSynchronization Transmit output
(FSX)
Thisoutputclock istheTransmit Framesynchroni-
zation pulse signal of the SSIA port which has
nominal frequency equal to the transmit sampling
frequency.Thispulseindicatesthebeginningofthe
16-bit serial words on the serial data input/output
port A.
Bit Clock Transmit output
(BCLKX)
This output pin providesthe serial bit clock for the
SSI port A. The BCLKXfrequencyequals V or V/2
timestheTransmitsamplingfrequency,depending
on the Bit Frame Select Input (BFRS).
SerialData Transmitinput
(TxDI)
This inputreceivesword-orientedserial data.Data
is loadedfromTxDIintothe TransmitShiftRegister
(TSRIN) on the falling edge of BCLKX and trans-
feredtotheTransmitBufferRegister(TBRIN)when
a complete16 bit word has been received. Data is
assumedto be receivedMSB first.
SerialData Transmitoutput
(TxDO)
This output sends word-oriented serial data. The
16 bit Data Word loaded in the Transmit Buffer
Register (TBROUT) is transfered to the Transmit
Shift Register (TSROUT) and clocked out of
TSROUT on the rising edge of BCLKX. Serial
words are transmittedMSB first.
Receive Frame Synchronizationoutput
(FSR)
This output clock is the Receive Framesynchroni-
zation pulse signal of SSI port B which has fre-
quency equal to the receive sampling frequency.
Thispulseisusedtoindicatethebeginningof serial
words on the serial data input/outputport B.
Receive Bit Clock output
(BCLKR)
This output pin providesthe serial bit clock for the
SSI port B. The BCLKR frequency is V times or
(V/2) times, selected by BFRS ) the receive sam-
pling frequency.
Receive SerialData input
(RxDI)
This inputreceivesword-orientedserial data.Data
isclockedfromRxDIinto theReceiveShiftRegister
(RSRIN) on the falling edge of BCLKR and trans-
feredtotheReceiveBufferRegister(RBRIN)when
a complete16-bit word has been received.Data is
assumedto be receivedMSB first.
Receive SerialData output
(RxDO)
This output sends word-oriented serial data. The
16-bit Data Word loaded in the Receive Buffer
Register (RBROUT) is transfered to the Receive
Shift Register (RSROUT) and clocked out of
RSROUT on the rising edge of BCLKR. Serial
words are transmittedMSB first.
STLC7545
8/53
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