參數(shù)資料
型號: STLC7545
廠商: 意法半導(dǎo)體
英文描述: Enhanced V.34 BIS Analog Front-End(單片模擬前端)
中文描述: 國際清算銀行增強.34模擬前端(單片模擬前端)
文件頁數(shù): 37/53頁
文件大?。?/td> 378K
代理商: STLC7545
VI - PROGRAMMABLE FUNCTIONS
(continued)
VI.2.4- Receive Bit Rate Clock Frequency Programming.DivisorRank
Table 31 :
ReceiveBit Rate Clock FrequencyProgramming. Divisor Rank
RxCR0 Register
Bit Rate Clock Frequency(Hz)
Rxclk = FQ/(N*R*S*T*CS) (1)
Divisor rank
RxCR3
D2
R3
-
-
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
RxCR3
D0
R2
-
-
0
0
0
0
1
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
1
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
N0
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R1
-
-
0
0
1
1
0
0
1
1
-
-
-
-
-
-
-
-
-
-
-
-
0
0
1
1
0
0
1
1
R0
-
-
0
1
0
1
0
1
0
1
-
-
-
-
-
-
-
-
-
-
-
-
0
1
0
1
0
1
0
1
S1
-
-
-
-
-
-
-
-
-
-
0
0
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
S0
-
-
-
-
-
-
-
-
-
-
0
1
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
T2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
1
1
1
1
-
-
-
-
-
-
-
-
T1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
1
1
0
0
1
1
-
-
-
-
-
-
-
-
T0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
1
0
1
0
1
0
1
-
-
-
-
-
-
-
-
N
R
S
T
3(INI)
4
8/7
6/5
4/3
1 (INI)
12/11
10/9
8/7
1
1
3
5 (INI)
7
4
8 (INI)
16
32
64
128
256
512
11/9
9/7
7/5
1
15/13
13/11
11/9
1 (INI)
INI : initial value
Note 1 :
The CS divisor is set by QSbit (D13) in TxCTRL word (QS = 1
CS = 16, QS = 0
CS = 8)
STLC7545
37/53
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