參數(shù)資料
型號: STLC7545
廠商: 意法半導體
英文描述: Enhanced V.34 BIS Analog Front-End(單片模擬前端)
中文描述: 國際清算銀行增強.34模擬前端(單片模擬前端)
文件頁數(shù): 23/53頁
文件大?。?/td> 378K
代理商: STLC7545
V - CIRCUIT PROGRAMMING
This section definesthe control and status words required to programthe STLC7545.
The circuit configurationis managedby the control words TxCtrl and RxCtrl and the SSIM, BFRS inputs.
The control words contain three fields :
- Mode Field
3 bits(D15-D13)
mode control bit
- AddressField
5 bits(D12-D8)
2 bitsfor CoeffRam address
3 bitsfor Control Registers address
- Data Field
8 bits(D7-D0)
ControlRegisters content
V.1 - MODE FIELD
Table 3 :
Mode Field
TxCtrl Word
D15
MS
0
1
-
D14
Stb
-
-
D13
QS
-
-
-
Select mode
Data Mode and Control Register access mode
Coefficient Loading Mode and Filter Data Memory Reset (INI)
Start bitfor Coefficient Loading or Reading. The loading is initiatedby a rising edge, i.e. a
logical one programmed after alogical zero.
XTAL10 Selected(INI) (CS equals 16 in bit chain clock)
XTAL11 Selected(CS equals8 in bit chain clock)
-
-
-
-
1
0
INI : initial value
V.2 - ADDRESSFIELD
V.2.1- RAM Address Field
Table 4 :
RAM AddressField
TxCtrl Word
D9
AD1
-
-
-
-
D15
MS
-
-
-
-
D14
Stb
-
D13
QS
-
-
-
-
D12
RA0
0
0
1
1
D11
RA1
0
1
0
1
D10
AD2
-
-
-
-
D8
AD0
-
-
-
-
RAM Address
RAM 1 (INI)
RAM 2
RAM 3
Not RAM access
INI : initial value
V.2.2- TransmitControlRegister Address Field
Table 5 :
TransmitControl RegisterAddress Field
Register Name
TxCtrl Word
(2)
D12
RA0
-
-
-
-
D15
MS
-
-
-
-
-
D14
Stb
-
-
-
-
D13
QS
-
-
-
-
D11
RA1
-
-
-
-
D10
AD2
0
0
0
0
1
1
D9
AD1
0
0
1
1
1
1
D8
AD0
0
1
0
1
1
0 (3)
TxCR0 (1)
TxCR1 (1)
TxCR2
TxCR3 (1)
None
EYE Pattern on TxI3
Notes :
1. A reset is generated when programming these registers (see III.5.2.1).
2. No registeraccess forthe non-specified code
3. In single interface mode only
STLC7545
23/53
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