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參數(shù)資料
| 型號(hào)： | STLC7545 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Enhanced V.34 BIS Analog Front-End(單片模擬前端) |
| 中文描述： | 國(guó)際清算銀行增強(qiáng).34模擬前端（單片模擬前端） |
| 文件頁(yè)數(shù)： | 18/53頁(yè) |
| 文件大?。?/td> | 378K |
| 代理商： | STLC7545 |
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(D0) D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
(D0)
Hz
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
BCLKX
(BCLKR)
TxDI
(RxDI)
TxDO
(RxDO)
Fsx
(Fsr)
7
Figure 5 :
SerialChannel Timing
IV - SERIAL INTERFACE OPERATION
Serial data transmission (reception) is initiated by
a frame synchro signal FSX (FSR). The Data is
clocked from TxDI (RxDI) into TSRIN (RSRIN) on
thefallingedge ofBCLKX(BCLKR)and transfered
totheTBRIN(RBRIN) registerwhenacomplete16
bitword has beenreceived.Data is assumedto be
received MSB first.
Serial data transmission (reception) output is initi-
ated by a frame synchro signal FSX (FSR). The
16-bit Data word is loaded into TSROUT
(RSROUT) and serially clocked out of TSROUT
(RSROUT) to TxDO (RxDO) on the rising edge of
BCLKX(BCLKR).
BCLKX(BCLKR)frequencycanbeprogrammedto
be either 64 or 128 (80 or 160) (90 or 192) times
Fsx (Fsr) using the Bit Frame Select (BFRS) input
pin. This mean that the frame contains four, five,
six, eight, ten or twelve time slots of 16 bits. The
time slotsusedfor circuitoperationare indicatedin
the next paragraph.
IV.1-DUALSERIALINTERFACEMODE
(SSIA,SSIB)
When SSIM is tied to V
DD
, both A and B portsare
functional : port A (SSIA) is dedicated to the Tx
channel and port B (SSIB) to the Rx channel. The
timingdiagram showingthedata formatis given in
Figures5 and 6.
Thetime-slotTXO1is dedicatedto RAMcoefficient
reading. The RAM coefficient is selected by the
address bits RA0 to RA1 in the TxCtrl word (see
Table 4). Reading is initiated by the rising edge of
Start bitStb (bit D14in Table3) in the TxCtrlword.
Note :
RxSig is also available in two time slot RxS1 and RxS2 on
the time slot TxO2 and TxO3 on SSIA(see section IV.2)
STLC7545
18/53
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