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參數(shù)資料
| 型號(hào)： | STLC7545 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Enhanced V.34 BIS Analog Front-End(單片模擬前端) |
| 中文描述： | 國(guó)際清算銀行增強(qiáng).34模擬前端（單片模擬前端） |
| 文件頁(yè)數(shù)： | 19/53頁(yè) |
| 文件大?。?/td> | 378K |
| 代理商： | STLC7545 |
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BCLKX
TxDI
TxDO
Hz
(Tx04)
(Tx03)
(Tx02)
(Tx01)
(Tx00)
(TxI0)
(TxI1)
(TxI2)
(TxI3)
(TxI4)
Unused
ITR3
ResSig
TxSig
RxTx
ITR2
TxCtrl
SSIA
Hz
SSIB
RxCtrl
BCLKR
RxDI
RxDO
(TRI0)
(TR00)
RxSig
ITR1
Reserved
(TR01)
(TRI1)
EYEY-EYEX
ITR2
Reserved
ITR3
Reserved
ITR1
Reserved
Reserved
(TRI2)
(TR02)
(TRI3)
(TR03)
(TRI4)
(TR04)
Add
5
Data
8
Mode
3
RAM
13
Add
8
Data
8
Fsx
Fsr
Unused
Unused
Unused
7
Figure 6 :
Serial ChannelTiming. Dual Port Mode
IV - SERIAL INTERFACE OPERATION
(continued)
IV.2- SINGLESERIAL INTERFACE MODE
When SSIM is tied to GND, only port A (SSIA) is
selected. In this case, port A carries both Tx and
Rx signal samples and control words at Tx sam-
pling rate (Fsx).
TheRxDI inputshouldbe tied to V
DD
. Sinceport B
is not functionalin this mode, the RxSig (synchro-
nizedto Fsr)will be availablein the two timeslots,
RxS1 and RxS2, synchronized to Fsx.
The reason for the two time slots is that the Fsr
couldbe differentinmagnitudeandphasefromthe
Fsx.
The status bit St0 and St1 are used to indicate
which of the RxS1and RxS2 are valid.Please see
the table following. For example, if Fsx = 9600Hz
and Fsr = 14400Hz both RxS1 and RxS2 could
carryvaliddata.Figure7 showsthetimingdiagram.
Thetime-slotTXO1is dedicatedto RAMcoefficient
reading. The RAM coefficient is selected by ad-
dress bits (RA0 to RA1) in the TxCtrl word (see
Table 4). Reading is initiated by the rising edge of
aStartbitStb(bitD14inTable3)intheTxCtrlword.
The time-slot TxI3 is dedicatedto the RxCtrl word
or the EYE-PATTERN,selected in the TxCtrl (see
Table 5).
Table 2
STATUS WORD IN TxO1 TIME SLOT
D0
St0
0
1
0
1
RxS1 and RxS2 (1)
D1
St1
0
0
1
1
Valid Data
None
None
RxS2
Note 1 :
The RxS1 sample precedes the RxS2 sample.
STLC7545
19/53
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