參數(shù)資料
型號(hào)： STLC7545
廠商： 意法半導(dǎo)體
英文描述： Enhanced V.34 BIS Analog Front-End(單片模擬前端)
中文描述： 國(guó)際清算銀行增強(qiáng).34模擬前端（單片模擬前端）
文件頁(yè)數(shù)： 16/53頁(yè)
文件大?。?/td> 378K
代理商： STLC7545
III - FUNCTIONALDESCRIPTION
(continued)
III.5.3 - ReceiveDPLL
The synchronization of the Rx countersdelivering
the Rx clocks (Figure 11) is performedby addition
or suppressionof masterclock periodsunder DSP
control.In thiscase,thephasecomparisonfunction
of the RxDPLL is implemented in the associated
DSP recovering the received symbols.
Twotypesof phaseshift controlareprovidedin the
STLC7545:
- a coarsephaselag of programmablemagnitude,
obtained from the suppression of 64 to 4096
successive masterclock transitions.This control
is to beused to reducetheRxDPLLlockingtime.
- a finephaselead or lagof programmablemagni-
tude (i.e. 8 to 32 master clock periods or one Tx
oversampling clock period) continuouslyused to
implementthe phasecontrolloop.(seeTable38).
Eachelementaryphaseshift,correspondingtoan
addition or a subtraction of one master clock
transition, is synchronized on an internal clock
with frequencyequal to the Rxoclk (128, 160 or
192 times the Rx sampling frequency Fsr). A
phaseshiftis ,therefore,alwayscompletedin less
than one Fsr period.
III.5.4 - ReceiveClocks
III.5.4.1-Internal Mode
The internal clock mode is selected when the pin
EOCMODE is tied to GND. In this mode the
STLC7545 provides three Rx synchronous pro-
grammable modemclocks :
- receivebit rate clock RxCLK
- receivebaud-rate clock RxRCLK
- receive highest synchronous clock, RxHSCLK
associated with the RxSYNC synchronization
pulse usefulto generateadditional clocks
The RxRCLK and RxHSCLK outputs can be dis-
abledwhen not used. The bit rate clock frequency
oftheRx modemcanbechosento bedifferentfrom
its Tx counterpart, provided Rx to Tx loopback is
not required. The Rx clock system also provides
theRxsamplingclockaswellasthebitandsynchro
clocks (BCLKR and FSR) used by the serial inter-
face B (SSI-B) described in sectionIV. The digital
reconstructionfilter implementedin the STLC7545
makes possible the choice of a receive nominal
sampling frequency different from the transmit
nominal sampling frequency. The counters of the
Rx clock system (Figure 11) are reset when pow-
ering on the STLC7545 and when the NLPR input
levelislow.Theycanalsobe reset,undersoftware
control, on the next falling edge of the RxRCLK
receive baud rate clock when the RxCR0, RxCR1
or RxCR3 register are accessed : this feature is
used to fix the phase of the bit rate clock with
respect to the baud rate clock, e.g. after each
modification of the bit or baud rate value. The
16/53
internally generated pulse resetting the Rx count-
ers isoutputat theRxSYNC pininorderto beused
with the RxHSCLKclock.
III.5.4.2- ExternalMode
The external clock mode is selectedwhen the pin
EOCMODE is tied the V
DD
. In this mode the user
must providethe STLC7545with the receiveover-
sampling clock. The internal DPLL can be used if
the external receive oversampling clock is gener-
ated by a divider synchronized by both the
RxHSCLKand RxSyncsignals.
III.6 - SERIALINPUT/OUTPUT
SYNCHRONOUS INTERFACES
The STLC7545has twoSynchronousSerial Inter-
faces ports, SSIA and SSIB. They allow inde-
pendent transmit and receive paths. Through the
two serialports, the STLC7545can talkto various
digital signal processors. The various serial inter-
facesignalsand internalregistersaregivenbelow:
SSI PORTA (SSIA)
- Transmit Frame Synchronizationoutput (FSX)
- Transmit Bit clockoutput (BCLKX)
- Transmit Serial Data input (TxDI)
- Transmit input Shift Register (TSRIN)
- Transmit input BufferRegister(TBRIN)
- Transmit output Shift Register(TSROUT)
- Transmit Serial Data output (TxDO)
SSI PORTB (SSIB)
- Receive Frame Synchronizationoutput (FSR)
- Receive Bit clock output(BCLKR)
- Receive Serial Data input (RxDI)
- Receive input Shift Register (RSRIN)
- Receive input Buffer Register(RBRIN)
- Receive output Shift Register (RSROUT)
- Receive Serial Data output(RxDO)
INPUT MODES
- SynchronousSerial InterfaceMode (SSIM)
- Bit Frame Rate Select(BFRS)
With SSIMinput,the usercan chooseeithersingle
interface mode or dual interface mode. In single
interface mode (section IV.2), only port SSIA is
operational.Whereas in dualinterfacemode(sec-
tion IV.1), both SSIA and SSIB ports are opera-
tional. These two ports carry data inside a
synchronous frame consisting of four/five or
eight/ten sixteen bit time slots (only the four first
time slots are used for transporting information.
SSIA port is synchronous to the Tx system clock
and SSIB port is synchronousto Rx systemclock.
The format of the signal samplescarried on these
portistwo’scomplementwithMSBsentorreceived
first.Asexplainedhereafteritisalsopossibletouse
the port A only to transfer the data between the
STLC7545 and the associated DSP.
STLC7545
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