參數(shù)資料
型號(hào)： STLC7545
廠商： 意法半導(dǎo)體
英文描述： Enhanced V.34 BIS Analog Front-End(單片模擬前端)
中文描述： 國(guó)際清算銀行增強(qiáng).34模擬前端（單片模擬前端）
文件頁(yè)數(shù)： 15/53頁(yè)
文件大小： 378K
代理商： STLC7545
III - FUNCTIONALDESCRIPTION
(continued)
III.5.1 - TransmitDPLL
Frequency control of the Tx clock system (Fig-
ure 10) is obtainedby performing additional up or
down countingsteps in thethree input dividers M,
N and P.
Theseelementaryphaseshiftsof onemasterclock
period are repeated at either the rate of the Fsx
clock, or half that rate, depending on the required
captureandtrackingranges(seeTable15and26).
The average updated frequency then varies be-
tweenthe followinglimits :
FQ - FSHIFT
≤
Faverage
≤
FQ + FSHIFT
Where FQ is the master clock frequency and
FSHIFT equalsFsx or Fsx/2(see table 26).
The TxDPLL phasecomparisonwhichdetermines
lead or lag decisions, is simply obtained by sam-
plingthesynchronizationclock,TxSCLKorRxCLK,
on the fallingedges of an internalclock takenfrom
thedivisionchain,FCOMP(seetable25).FCOMP
frequency must be an integer submultiple of the
synchronization clock. This frequency determines
the Tx jitter magnitude. In V.34 synchronization
mode FCOMP is equal to 2400Hz, and in 7544
mode the synchronization clock FCOMP can be
chosentobeequaltothebaudratefrequency.Only
phase shifts of the same sense (lead or lag) are
performedduringeach FCOMPperiod.The actual
phaseshiftsduringFCOMPperiodaregivenbythe
ratio
FSHIFT/FCOMP
These phase shifts are performed at the inputs of
the M,N, and P dividers to lock the DPLL to the
synchronisationsignal (seeTable 22).
Ifthereisno transitiononTxSCLKPin,theTxDPLL
is free running.
To phase lock the TxDPLL there must be transis-
tion on TxSCLK input within FCOMP period when
programming TxCR2 register.
The Tx clock system may also run freely without
any phase shift. In this case, the TxSCLK input is
no longeractive.
The
DPLL capture and tracking range equals
±
FSHIFT/FQ. They have to be greater than
±
200ppm to comply with CCITT recommenda-
tions.FSHIFT=Fsx/2minimizesthe jitter.Because
of this,there is a trade-offbetweenhigher capture
and trackingranges and lower jitter.
Ex : FQ = 36.864MHzand FSHIFT = 9600Hz.
Capture and tracking range =
±
FSHIFT/FQ
=
±
9600Hz/36.864MHz=
±
260ppm
III.5.2. Transmit Clocks
III.5.2.1- InternalMode
The internal clock mode is selected when the pin
EOCMODE is tied to GND. In this mode the
STLC7545 provides three Tx programmable syn-
chronous modemclocks :
- a transmit bit rate clock TxCLK
- a transmit baud rate clock TxRCLK
- a transmit highestsynchronousclock TxHSCLK,
associated with the TxSYNC synchronization
pulse, useful to generate additional clocks (e.g.
extra divisors)if needed.
The outputs of the TxRCLK and TxHSCLK clocks,
can be disabled when not used, but in 7544 syn-
chronisation mode a correct baud rate frequency
must be programmed as the FCOMP clock fre-
quencydependson it.
The Tx clock system provides the sampling and
oversamplingclocks aswell as thebit and synchro
clocks (BCLKX and FSX) used by the serial inter-
face A (SSI-A) describedin section IV.
Thecountersof theTxclocksystem(Figure10)are
automatically reset when powering-on the
STLC7545 and when the NLPR input level is low.
They can also be reset, under software control,
during the followingconditions:
(1) on thenext fallingedgeof theTxSCLKterminal
clock or of the RxCLK receive bit rate clock
(SST bit Table 22).
(2) onthenextfallingedgeof theTxRCLKtransmit
baud rate clock(baudchainclockreset)and in
the next falling edge of FCOMP (bit chain
clocks) when TxCR0, TxCR2 or TxCR3
register is accessed.
The case (1) gives the capability to speed-up the
Tx DPLL synchronization; the case (2) is usefulto
fixthephaseof the bitrate clockwithrespectto the
baudrateclock,inparticularaftereachmodification
of thebit or baud rate value.
The internally generated pulse resetting the Tx
counters is output at the TxSYNC pin in order to
synchronizeexternalfunctionsusingtheTxHSCLK
clock.
III.5.2.2- ExternalMode
The external clock mode is selectedwhen the pin
EOCMODEis tiedtotheV
DD
. Inthismodethe user
mustprovidethe STLC7545with thetransmitover-
sampling clock. The internal DPLL can be used if
the externaltransmit oversampling clock is gener-
ated by a divider synchronized by both the
TxHSCLK and TxSync signals.
STLC7545
15/53
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