參數(shù)資料
型號: STLC7545
廠商: 意法半導體
英文描述: Enhanced V.34 BIS Analog Front-End(單片模擬前端)
中文描述: 國際清算銀行增強.34模擬前端(單片模擬前端)
文件頁數(shù): 20/53頁
文件大?。?/td> 378K
代理商: STLC7545
BCLKX
TxDI
TxDO
Hz
(Tx03)
(Tx02)
(Tx01)
(Tx00)
(TxI0)
(TxI1)
(TxI2)
(TxI3)
RxS2
RxS1
ResSig
TxSig
RxTx
TxCtrl
SSIA
Add
5
Data
8
Mode
3
St
2
1
RAM
13
RxCtrl or
Eye-pattern
Add 8
EYEY
Data 8
EYEX
Fsx
(TxI4)
(Tx04)
7
Figure 7 :
SerialChannel Timing. Single PortMode
BCLKX
TxDI
(TxI0)
(TxI1)
(TxI2)
(TxI3)
TxCtrl
SSIA
Add
5
Data
8
Mode
3
BCLKX
TxDI
(TxI0)
(TxI1)
(TxI2)
(TxI3)
TxCtrl
Add
5
Data
8
Mode
3
Unused
Coeff 1
(a). 1st Frame
Coeff2
Coeff38
(b). 13th Frame
Coeff 36
1st Frame
13th Frame
Fsx
Fsx
Coeff 37
(TxI4)
(TxI4)
7
Figure 8 :
CoefficientLoadingMode
IV - SERIAL INTERFACE OPERATION
(continued)
IV.3- COEFFICIENT LOADING MODE
The Coefficient Loading Mode is selected by the
Mode Selectbit (MS)in theTxCtrlWord (Table3).
When the MS bit is a logic ”1” the loading mode is
selected. The IIR RAMS (RAM1 to RAM3) are
selected in the TxCtrl word by two address bits
(RA0 to RA1). Each coefficient RAM stores 38
coefficients of 13 bits. Therefore the size of the
coefficient RAM is 38 x 16 bits. The first frame
transfers2 coefficientsand the12 followingframes
each transfer3 coefficientsinto theselectedRAM,
as shown in Figure 8. The transfer is initiated by
the risingedge of theStartbit coefficientStb which
is loadedintothe TxCtrlword.Whenthe coefficient
loading mode is selectedall data pathare fixed to
zero.
Notes :
1. Coefficient loading is the same forboth dual and single
interface modes.
2. In coefficient loading mode , the EYE-PATTERN (time
slot TxI3) (and the RxCtrl in a single serial interface)
cannot be accessed
STLC7545
20/53
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