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參數(shù)資料
| 型號： | STLC7545 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Enhanced V.34 BIS Analog Front-End(單片模擬前端) |
| 中文描述： | 國際清算銀行增強(qiáng).34模擬前端（單片模擬前端） |
| 文件頁數(shù)： | 21/53頁 |
| 文件大小： | 378K |
| 代理商： | STLC7545 |
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IV - SERIAL INTERFACE OPERATION
(continued)
IV.4- COEFFICIENT READING
Coefficientreadingis selectedinDATAmodeonly,
i.e. when the Mode Select bit (MS) in the TxCtrl
word is tied to logical 0. The IIR RAMS (RAM1 to
RAM3) are selected in the TxCtrl word by two
address bits (RA0 to RA1). The 38 coefficients of
13 bitsareavailable,one per frame,in thetimeslot
TxO1 on the output Tx port A (see Figures 6, 7).
The reading is available on the rising edge of the
Start bit Stb loaded into the TxCtrl word. The first
coefficient is output with one frame of delay on
TxO1.
IV.5- CRYSTALSELECTION (XTAL10,XTAL11)
For applicationneeding different or higher symbol
rates,theusercan softwareselect differentmaster
clock frequencies for the STLC7545. Two XTAL
inputs are provided for this purpose. The active
XTALinputis selectedin thetime slotTxI1withthe
Quartz Select bit (QS). It is mandatory to shortcir-
cuitthe XTAL10and XTAL11inputswhen a single
externalcrystal or clock generator is used.
IV.6- FRAMEFREQUENCY PROGRAMMING
When using the nominal master clock frequency,
the frame frequency can be from 7200Hz to
16000Hz (see Tables 15 and 32). Whenever the
frame frequency Fsx (Fsr) is modified, the data to
theSTLC7545 during that frameshould be highin
the time slots TxI1 (RxI1), TxI2 (RxI2) and TxI3
(RxI3).ThisisbecausetheBCLKX(BCLKR)during
that frame may not be correct. Therefore, when-
ever the Fsx (Fsr) is changedthe user hasto send
informationtotheSTLC7545afteroneframedelay.
IV.7 - INITIALIZATION AND LOW-POWER
RESETMODE
Internalpower-on circuitry automaticallyresets the
DPLL, the clockgeneratorcounters,and initializes
the internal control registers. The clocks affected
arethesymbolclock,thebitclockandthe sampling
clock. The initial status of these registers is given
in the PROGRAMMABLE FUNCTIONS section.
The transmit attenuator is initialized to an infinite
attenuationmode(seeTable24)toavoidthetrans-
missionof undesirablesignals on the phoneline.
Duringhardwarelowpower reset(NLPRpin istied
to GND),the input of theinverter (acrossthe crys-
tal) will be high (DV
DD
), the DPLLs and the clock
generator counters are initialized, all the analog
circuitryisplacedinlow-powermodeand theXTAL
oscillator is stopped.
Access to the circuit is disabled during reset until
the clockoscillator starts. The durationof thereset
time can be increased by connecting the NLPR
input to an external RC timeconstant as indicated
in Figure9.
In normal operation the NLPR input is used to
control the LowPower mode. When NLPR is not
used, it must be tied to V
DD
.
STLC7545
21/53
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