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參數(shù)資料
| 型號： | STLC7545 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Enhanced V.34 BIS Analog Front-End(單片模擬前端) |
| 中文描述： | 國際清算銀行增強.34模擬前端（單片模擬前端） |
| 文件頁數(shù)： | 7/53頁 |
| 文件大?。?/td> | 378K |
| 代理商： | STLC7545 |
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I - PIN DESCRIPTION
(continued)
I.3 - PIN FUNCTION
I.3.1- Power Supply
(9 Pins)
Analog V
DD
Supply
(AV
DD
)
This pin is the positive analog power supply
(+5V
±
5%) for the Transmit and the Receive sec-
tions. It is not internally connected to digital V
DD
supply(DV
DD1-3
).
Digital V
DD
Supply
(DV
DD1
,DV
DD2
,DV
DD3
)
These pins are the positive digital power supply
(3.5V to 5.25V) for Transmit and Receive digital
internalcircuitry.
Analog Ground
(AGNDT,AGNDR)
These pins are the analog ground return of the
analog Transmit (Receive)section.
Digital Ground
(DGND1,DGND2,DGND3)
These pins are the ground connectionsfor Trans-
mit and Receiveinternal digital circuitry.
Note 1 :
To obtain published performance, the analog V
DD
and
DigitalV
DD
should bedecoupledwithrespecttoAGNDand
DGND, respectively. The decouplingis intended to isolate
digital noise from the analog section; decoupling
capacitorsshould be as closeas possibletothe respective
analog and digital supply pins.
Note 2 :
All the groundpins must be tied together. In the following
section, theground andsupply pins are referedtoas GND
and V
DD
, respectively.
I.3.2- Clock and Control Signals
(16 Pins)
ExternalClock/CrystalInputs
(XTAL10,XTAL11)
XTAL10and XTAL11inputs must be tiedto exter-
nalcrystal(s)or externalclock(s).These inputsare
selected from the TxCtrl register. The maximum
clockrateis 38MHz.XTAL10is thedefaultExternal
Clock/Crystal input. It is mandatory to shortcircuit
XTAL10andXTAL11whenasingleexternalcrystal
or clock generator is used. The nominal master
clockfrequencyis 36.864MHz(this frequencyand
the frequency25.8048MHzare well suited for the
V.34 application) but the onchip amplifier is de-
signed for a parrallel crystal oscillator with a fre-
quency equal to 18.432MHz. The other master
clocks frequencies(18.432MHz,25.8048MHzand
29.4912MHz) are well suited for the well known
CCITTrecommendations(V.21 through V.32bis).
Crystal Outputs
(XTAL2)
This output is to be tied to one or two external
crystals(seeFigure1). If anexternalclock is used,
XTAL2 should be left open circuit.
Low powerand Reset Input
(NLPR)
This pin , when low, synchronizes the STLC7545
clocksystemand puts it in low powermode. NLPR
pin must be tied to V
DD
during normal operation.
Access to the chip is disabled during power-on
reset untiltheclockoscillator starts.Thereset time
durationcan beincreasedbyconnectingtheNLPR
inputto anexternalRCnetwork(seeFigure9).The
Low-PowerReset Mode is activated when thispin
is tied to GND (Operation of all clocks and the
analog section is stopped).
TransmitSynchronizationClockInput
(TxSCLK)
This pin can be connectedto an externalterminal
clock to phase-lock the internal transmit clocks. It
can be disabledundersoftwarecontrolto allowthe
Tx DPLL to free run or phase lock on the Rx clock
system. To phase lock the TxDPLL there must be
transition on TxSCLK input within FCOMP period
when programming TxCR2 register.
Transmit Bit Rate Clock Output
(TxCLK)
This pinoutputsthe synchronoustransmitbit clock
selectedfor the MODEM.
Transmit Baud Rate Clock Output
(TxRCLK)
This pin, when the bit D4 within receive register
RxCR3 is set to 0, outputsthe synchronoustrans-
mit baudrate clock(initialstate).WhenbitD4 isset
to 1 this pin outputs the frequency comparison
signal FCOMP (used by the TxDPLL in both 7544
mode and V.Fast synchronization) when bit 0 of
RxCR1 is set to 0 this output is disabled.
Transmit Synchronization Pulse Output
(TxSYNC)
This pinoutputsthe synchronizationtransmitreset
pulsewhena softresetis appliedto theSTLC7545.
Combined with TxHSCLK clock it can be used to
externallyprovideanysynchronoustransmitclock.
Transmit Highest Clock Output
(TxHSCLK)
This pin outputsthe highest synchronoustransmit
clock to provide any externalor multiplexing clock
when bit 0 of RxCR1 is set to 0 this output is
disabled.
Transmit OversamplingClock input
(TxOCLK)
This inputcanbe connectedtoanexternalclockto
provide the chip with the over-sampling clock, de-
pendingon theExternalOversamplingMode input
(EOCMODE). In normal mode this pin should be
static(tied to GND or V
DD
).
Receive Bit Rate Clock Output
(RxCLK)
This pin outputs the synchronousreceivebit clock
selectedfor the MODEM.
Receive Baud Rate Clock Output
(RxRCLK)
This pin outputs the synchronous Receive baud
rateclockwhenbit0ofRxCR1issetto0thisoutput
is disabled.
STLC7545
7/53
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