參數(shù)資料
型號: S1D13706
廠商: 愛普生(中國)有限公司
英文描述: S1D13706 Embedded Memory LCD Controller
中文描述: S1D13706 LCD控制器的嵌入式存儲器
文件頁數(shù): 81/152頁
文件大?。?/td> 1784K
代理商: S1D13706
Epson Research and Development
Vancouver Design Center
Page 81
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
1.
2.
3.
4.
5.
6.
Ts
t1typ
t2typ
t3typ
t7typ
t8typ
= pixel clock period
= (REG[22h] bits 7-0) + 1
= ((REG[12h] bits 6-0) + 1) x 8
= (REG[20h] bits 6-0) + 1
= ((REG[16h] bits 7-0) + 5) - ((REG[22h] bits 7-0) + 1)
= ((REG[14h] bits 6-0) + 1) x 8
Figure 6-33: 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing
Table 6-26: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Parameter
Min
Typ
14
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
FPLINE start position
Horizontal total period
FPLINE width
FPSHIFT period
Data setup to FPSHIFT rising edge
Data hold from FPSHIFT rising edge
Horizontal display start position
Horizontal display period
FPLINE rising edge to GPIO3 rising edge
GPIO3 pulse width
GPIO1(GPIO0) pulse width
GPIO1 rising edge (GPIO0 falling edge) to FPLINE rise edge
GPIO2 toggle edge to FPLINE rise edge
400
440
1
1
0.5
0.5
60
320
59
1
353
5
11
Table 6-27: 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing
Symbol
t1
t2
t3
t4
Parameter
Min
245
Typ
Max
330
Units
Lines
Lines
Lines
Lines
Vertical total period
Vertical display start position
Vertical display period
Vertical sync pulse width
4
240
2
t1
t4
FPFRAME
(SPS)
t2
t3
LINE1
LINE2
LINE240
FPDAT[17:0]
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