參數(shù)資料
型號： S1D13706
廠商： 愛普生（中國）有限公司
英文描述： S1D13706 Embedded Memory LCD Controller
中文描述： S1D13706 LCD控制器的嵌入式存儲器
文件頁數(shù)： 30/152頁
文件大?。?/td> 1784K
代理商： S1D13706
Page 30
Epson Research and Development
Vancouver Design Center
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
4.6 LCD Interface Pin Mapping
Note
1
GPIO pins must be configured as outputs (CNF3 = 0 at RESET#) when the HR-TFT or
D-TFD interface is selected.
2
These pin mappings use signal names commonly used for each panel type, however
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
Section 6.4, “Display Interface” on page 56.
3
When the HR-TFT interface is selected (REG[10h] bits 1-0 = 10), this GPO can be
used to control the HR-TFT MOD signal. Note this is not the same signal as the
S1D13706 DRDY(MOD) signal used for passive panels.
Table 4-9: LCD Interface Pin Mapping
Pin Name
Monochrome Passive
Panel
Color Passive Panel
Color TFT Panel
Single
Single
Others
Sharp HR-
TFT
18-bit
SPS
LP
DCLK
no connect
R5
R4
R3
G5
G4
G3
B5
B4
B3
R2
R1
R0
G2
G1
G0
B2
B1
B0
PS
CLS
REV
SPL
GPIO4
(output only)
GPIO5
(output only)
GPIO6
(output only)
MOD
3
Epson
D-TFD
1
18-bit
DY
LP
XSCL
GCP
R5
R4
R3
G5
G4
G3
B5
B4
B3
R2
R1
R0
G2
G1
G0
B2
B1
B0
XINH
YSCL
FR
FRS
4-bit
Format 1
8-bit
Format 2
8-bit
FPFRAME
FPLINE
FPSHIFT
16-Bit
4-bit
8-bit
9-bit
12-bit
18-bit
FPFRAME
FPLINE
FPSHIFT
DRDY
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
FPDAT16
FPDAT17
GPIO0
GPIO1
GPIO2
GPIO3
MOD
D0
D1
D2
D3
D4
D5
D6
D7
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
FPSHIFT2
D0 (B5)
2
D1 (R5)
2
D2 (G4)
2
D3 (B3)
2
D4 (R3)
2
D5 (G2)
2
D6 (B1)
2
D7 (R1)
2
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
MOD
DRDY
R3
R2
R1
G3
G2
G1
B3
B2
B1
R0
driven 0
driven 0
G0
driven 0
driven 0
B0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
driven 0
driven 0
driven 0
driven 0
D0
D1
D2
D3
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
driven 0
driven 0
driven 0
driven 0
D0 (R2)
2
D1 (B1)
2
D2 (G1)
2
D3 (R1)
2
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
D0 (G3)
2
D1 (R3)
2
D2 (B2)
2
D3 (G2)
2
D4 (R2)
2
D5 (B1)
2
D6 (G1)
2
D7 (R1)
2
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
D0 (R6)
2
D1 (G5)
2
D2 (B4)
2
D3 (R4)
2
D8 (B5)
2
D9 (R5)
2
D10 (G4)
2
D11 (B3)
2
D4 (G3)
2
D5 (B2)
2
D6 (R2)
2
D7 (G1)
2
D12 (R3)
2
D13 (G2)
2
D14 (B1)
2
D15 (R1)
2
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
R2
R1
R0
G2
G1
G0
B2
B1
B0
R5
R4
R3
G5
G4
G3
B5
B4
B3
R2
R1
R0
G2
G1
G0
B2
B1
B0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
RES
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
DD_P1
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
YSCLD
GPO
CVOUT
PWMOUT
GPO (General Purpose Output)
GPO
CVOUT
PWMOUT
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