參數(shù)資料
型號: S1D13706
廠商: 愛普生(中國)有限公司
英文描述: S1D13706 Embedded Memory LCD Controller
中文描述: S1D13706 LCD控制器的嵌入式存儲器
文件頁數(shù): 129/152頁
文件大?。?/td> 1784K
代理商: S1D13706
Epson Research and Development
Vancouver Design Center
Page 129
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
bits 7-0
CV Pulse Burst Length Bits [7:0]
The value of this register determines the number of pulses generated in a single CV Pulse
burst:
Number of pulses in a burst = (ContentsOfThisRegister) + 1
bits 7-0
PWMOUT Duty Cycle Bits [7:0]
This register determines the duty cycle of the PWMOUT output.
CV Pulse Burst Length Register
REG[B2h]
Read/Write
CV Pulse Burst Length Bits 7-0
7
6
5
4
3
2
1
0
PWMOUT Duty Cycle Register
REG[B3h]
Read/Write
PWMOUT Duty Cycle Bits 7-0
7
6
5
4
3
2
1
0
Table 8-19: PWMOUT Duty Cycle Select Options
PWMOUT Duty Cycle [7:0]
00h
01h
02h
...
FFh
PWMOUT Duty Cycle
Always Low
High for 1 out of 256 clock periods
High for 2 out of 256 clock periods
...
High for 255 out of 256 clock periods
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